The 10 Most Common EMC Challenges in a PCB Design
Improve your PCB designs and avoid costly respins due to EMC test failures by learning some basic design techniques and applying modern EMC analysis software.
Designing Printed Circuit Boards (PCBs) presents numerous challenges, including size constraints, mechanical integration, thermal considerations, and power efficiency. Adding to this complexity is electromagnetic compatibility (EMC), which introduces additional hurdles when bringing a new product to market.
EMC covers a broad range of electromagnetic phenomena that includes the unintentional generation, propagation, and reception of electromagnetic energy. EMC issues can prevent the proper operation of your PCB or interfere with other nearby electronic systems.
Figure 1. Identifying EMC issues during the PCB design phase. Image used courtesy of Mitai (click to enlarge)
This article aims to address the most prevalent EMC issues encountered during PCB design and offers practical strategies to minimize their impact.
The board stack-up defines and arranges the conductive and non-conductive layers within a PCB. These layers are defined by the following properties:
- Conductive layers: number, order, material, and copper weight.
- Non-conductive layers: number, order, dielectric material, and height.
The PCB can range from a basic, single-layer design to a very complex, multilayer system. Most PCBs today have 4 layers or more due to the increasing demands for high-frequency signals and small component sizes.
A suitable arrangement of these layers can provide many benefits to the EMC and signal integrity behavior of a PCB. This renders the board stack-up one of the most critical decisions when designing a new PCB.
Careful planning of the stack-up—proper layer ordering, grounding, and shielding—can minimize crosstalk and impedance mismatch. Modifying the stack-up late in the PCB design cycle can be particularly difficult and time-consuming. Therefore, defining a robust PCB stack-up configuration during the early stages of the design can save you significant time and effort.
PCB traces inherently possess finite resistance, inductance, and capacitance. This unintentional impedance is known as parasitic impedance. Keeping this undesirable impedance as low as possible is crucial for signal Integrity and EMC.
In your PCB designs, you can minimize parasitic impedance by using short and wide connections between components. Careful component placement also plays a pivotal role.
All currents leave a source and return to it, making a circuit loop. The return currents always follow the path with lowest impedance. At low frequencies, this path is determined as the path with the lowest resistance. At medium and high frequencies, the return currents follow the path of the least inductance.
Figure 2. Printed circuit board traces. Imaged used courtesy of Adobe
The return path needs to be as short as possible to avoid undesired emissions and coupling. It can be achieved following these basic guidelines:
- Keep components as close as possible; particularly those that drive signals with short rise times.
- Use wide ground planes to keep the inductance as low as possible.
- Use a board stack-up that keeps the return path short.
- Avoid gaps in the ground planes.
Ground Connections and Reference Planes
Ground serves as a stable reference point for the electrical signals. Making the connections to the ground plane through a long track or a poor copper plane directly introduces unintended parasitic effects.
A short route for the current return to ground ensures a low-impedance return path. It also minimizes the potential of creating ground loops, which can generate radiated emissions and degrade signal integrity and EMC.
Reference planes are big copper areas used to create a return path for ground and to provide a reference to high-frequency signals. They are needed for transmission lines and are a very efficient, cost-effective solution to keep emissions under control.
It is very common to see PCBs filled with vast copper areas in the different layers. However, these copper areas have a non-zero impedance, so they introduce an inductance, capacitance, and resistance. In order to minimize the impact of this non-ideal impedance, the return path must be as electrically short as possible. It also means that connections between the different ground planes on different PCB layers must also be designed to keep the impedance low.
A low impedance between planes can be achieved using stitching vias. By adding uniformly distributed vias along the reference planes, the impedance between them will be dramatically reduced. This, in turn, reduces the parasitic effects. The biggest advantage of this technique is that it does not increase the price or the complexity of the PCB.
Figure 3. Via stitching is crucial for a low impedance ground path. Image used courtesy of Mitai (click to enlarge)
Placing long traces close to each other can have a negative effect on the signal integrity and EMC. The fields generated by one trace interact with adjacent traces, causing unwanted signal coupling. This phenomenon is known as crosstalk.
To reduce crosstalk:
- Increase the distance between adjacent traces.
- Reduce the distance between traces and the reference plane.
- Add a ground plane between signal layers to contain the fields (shielding).
While the first option is easy to implement, it can increase the size of the board. The second method can strongly impact other aspects of the PCB, such as the manufacturing or impedance control of high-speed traces.
Other techniques to deal with crosstalk include avoiding traces routed parallel to each other, locating components away from I/O interconnects, and isolating high-noise emitters onto different layers within the stack-up.
It is quite common for PCBs to be interconnected with other PCBs, power units, sensors, or other external systems. They may also be exposed to contact with people. Each of these can create electrostatic discharge (ESD) events. These discharges are very short in time, but very energetic.
It is a good practice, or even compulsory if the board needs to pass immunity tests, to add protection elements to each connector or element that is entering or leaving the board, especially if it is going to be touched by humans.
These protection elements can be:
- Transient voltage suppressors (TVS) that clamp transient events to avoid permanent damage to the board components.
- Metal-oxide varistors (MOV) that redirect current away from sensitive components when voltage spikes are detected.
- Thermistors that increase (or decrease) their resistance in response to temperature changes to provide self-regulating protection. These are available with positive and negative temperature coefficients.
Microcontrollers, communication modules, and other active components can act as active noise sources. Decoupling capacitors (also known as bypass capacitors) can mitigate the effects of this noise.
Figure 4. Place decoupling capacitors near ICs on a PCB. Image used courtesy of Adobe
The decoupling capacitors filter out the high-frequency noise and provide a low-impedance return path for high-frequency current. Special care needs to be taken for good decoupling:
- Place decoupling capacitors very close to the ICs to keep the return current path as short as possible.
- Make the connection to ground as short as possible to reduce the amount of parasitic inductance.
- Choosing capacitors with low Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR).
Figure 5. Values and placement of decoupling capacitors are critical for proper functioning. Image used courtesy of Mitai (click to enlarge)
Traces Close to the Board Edges
Traces carrying fast digital signals generate high alternating fields. If these traces are too close to a board edge that has no shielding, these fields can leave the board, generating unintended radiated emissions.
Assuming that the board has a solid reference plane, follow these guidelines to reduce the amount of unintended radiation:
- Move the traces toward the internal area of the board.
- Add a via fence around the whole board to shield it.
Figure 6. Fast-switching signals near the PCB edge can generate radiated emissions. Image used courtesy of Mitai (click to enlarge)
Differential pairs are a special type of transmission line where the signal and the return are routed in parallel. Differential pairs need to be routed with a constant impedance to avoid reflections and with the same length to avoid signal skew.
To keep the differential impedance under control:
- Control the board stackup by proper selection of the dielectric height and properties.
- Place solid ground planes near the differential pairs.
The formulas for calculating the impedance of transmission lines are valid as long as the reference (ground) plane is under the signals. A lack of a ground plane or a gap in it will generate an impedance mismatch, generating losses and reflections.
Get EMC Recommendations for Your PCB Design
Designing EMC-compliant PCBs is a complex challenge. By following the recommendations in this article, you can improve your skills as a PCB designer and move towards getting EMC right the first time!
To also help with our PCB design, Mitai Augmented AI can quickly identify potential EMC issues in your layout and provide expert recommendations. Simply upload your design in a number of common industry formats and Mitai will help optimize your design for EMC testing.
Figure 7. Mitai Augmented AI tool for EMC design. Image used courtesy of Mitai
Mitai is a digital EMC solutions platform designed for companies and individuals to effortlessly identify, analyze, and resolve EMC issues. It can help ensure first-time EMC compliance to minimize costly iterations in board design and accelerate your product development. Unlike many other traditional EMC solutions in the market, Mitai offers an exceptionally reliable and affordable online platform that combines augmented AI analysis, EMC expert consultations, and a network of pre-compliance and certified EMC labs to ensure your product passes EMC tests.
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