BCD Adder
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Details
Category: Arithmetic Core
Created: September 02, 2016
Updated: November 19, 2019
Language: VHDL
Other project properties
Development Status: Planning
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
The goal of this project is to design a generic BCD adder that can adds two BCD inputs and a carry in to produce a BCD sum and a carry out.
