FPGA-based Median Filter Architecture

FPGA-based Median Filter Architecture


Category: Arithmetic Core

Created: March 18, 2014

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL


This implementation project proposes a practical implementation of a Median Filter architecture focused in low-cost FPGA devices. The architecture is based on the research presented in the following paper: http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/ENG6530_RCS_html_dr/outline_W2014/docs/PAPER_REVIEW_dr/2013_dr/GRAD_drFPGAbasedMedianFilter.pdf

Sorry, but we do not have time to develop a proper architecture document. However the paper presents a brief and at the same time complete description for this implementation design.