Generic Galois LFSR Generator in MyHDL

Generic Galois LFSR Generator in MyHDL


Category: Arithmetic Core

Created: January 11, 2018

Updated: January 27, 2020

Language: Other

Other project properties

Development Status: Beta

WishBone compliant: No

WishBone version: n/a

License: LGPL


An n-width Galois LFSR generator written in MyHDL with max-cycle tap positions for selected widths.

An table of taps for selected widths is used to generate n-width Galois LFSR modules. The table data is sourced from the work of Roy Ward and Tim Molteno, currently available at

Users of the python script may generate a module of their own specification. Register width and starting value are specified.

Samples modules with randomized starting values are provided for each width in the project's tap table, so python is not actually needed in order to use take advantage of the efforts of this small project. Sample modules are available for both Verilog and VHDL.


- Use python to implement an algorithm for finding max-cyle taps. One such method is described by Ward and Molteno

- Allow users to specify module parameters from the command line when generating new modules - eg "python --width=8 init=44" - Currently, users must edit the python scripts to customize module output.