Cheap Ethernet Interface for FPGAs

Cheap Ethernet Interface for FPGAs


Category: Communication Controller

Created: August 31, 2012

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Beta

WishBone compliant: No

WishBone version: n/a

License: LGPL


Cheap Ethernet interface
Realization of Ethernet interface and protocols optimized for minimal external components and FPGA resources.
FPGA may connecting through transformer or directly to twisted pairs (on your own risk).

- 10BASE-TX interface (10 MBit/sec) full-duplex (thanks to
- Base functional of ARP (reqest, reply), ICMP (reply), UDP protocols (server, client).
- Maximum packet size is 1 kb (fragmentation not supported).

Required 50MHz/48Mhz and 20MHz clocks, 8kbit block memory, ~800 slices.
Tested on Spartan 3E 500 with transformer and direct connection to twisted pair.