RS232 with Buffer State and Wishbone Interface
Details
Category: Communication Controller
Created: January 13, 2013
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Alpha
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Two wire RS232 communication module capable of 5, 6, 7, 8 bit word communication, Parity bit, Parity bit Polarity, 1 and 2 stop bits. Integrated with transmit and receive buffer controlled through a WishBone interface. Besides the WishBone interface auxiliary signals are provided for Buffer status and can be used for interrupt driven routines.
