JTAG Master in VHDL

JTAG Master in VHDL


Category: Communication Controller

Created: May 26, 2010

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: LGPL


This is a JTAG Master written in VHDL. It's simulated and tested with XC9500 and the jtag slave from opencores (http://opencores.orgproject,jtag)