PYRAMID Algorithm Integer Multiplier Unit

Before You read
This is a brief overview of the article about the series of multiplication algorithms. For comparison and estimation of proposed algorithms please refer to the full article... (see PDF file from downloads.) Overview
Operation of multiplication is very important in microelectronics. Each modern microprocessor has this operation within its instruction set, and advanced microprocessors have special multiplication units, that perform multiplication during 1 synchronization period(cycle). Especially valuable multiplication is in DSP processors, where it is practically main operation. Performance of any DSP processor is defined with delays in it MAC (multiply and accumulate) unit. So efficiency of multiplication is very important.

Methodology Overview.
The idea of algorithms is as follows. Unsigned multiplicands A and D may be represented in following form: A*D = (B * 2ⁿ + ó) * (E * 2ⁿ + F), where n – any number that is satisfied with following conditions:

1. 2ⁿ < á;
2. 2ⁿ < D;
3. ó < 2ⁿ;
4. F < 2ⁿ.

«Pyramid» algorithm.
Have a look at basic formula A*D = (B * 2ⁿ + ó) * (E * 2ⁿ + F). In case n=m-1, C and D have dimension of one bit. This basic formula is applied recursively to all further multiplicands. As a result dimension of multiplicands is decreased by one at every iteration. That is why the algorithm was named as “pyramid”.

Modified «pyramid» algorithm.
Modified «pyramid» algorithms is differ from prototype with value of n = m-2 and with dimension of operands C É D equal to 2 bits. As may be seen Modified pyramid algorithm implementation such small change gives valuable results improvement for area allocation.

Features

"Pyramid" integer multiplication unit characteristics The algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithms.
 

,

"Optimized pyramid" multiplication IP core characteristics The algorithm was written in VHDL, synthesized within Synopsys Design Compiler on 0.35u CMOS library. The data of the allocation areas are given only for a combinational part of algorithms.
 

,

Links

These cores are developed and provided by ASIC reseach department member of DeverSYS Corp., Vladimir V.Erokhin. More usefull fundamental (and not only) FREE IP Cores can be found at DeverSYS web www.deversys.com.