Quadrature Decoder / Counter

Quadrature Decoder / Counter


Category: Communication Controller

Created: December 23, 2003

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: GPL


This is a very simple project for reading a quadrature device, such as an optical encoder. The counter is initialized to zero, and then counts up and down when valid quadrature is present at the inputs


- Simple VHDL for beginners; well documented; shows use of hierarchical design.
- Count limited only by bit length of counter vector; simple to count very large values
- VHDL Implementation of Xilinx application note #012 (xapp012.pdf)
- NPL project file for immediate evaluation in Xilinx ISE/Webpack tools
- Questions/Comments: http://www.franks-development.com

Project Contents

- QuadratureCounter.vhd, top-level VHDL
- QuadratureDecoder.vhd, sub-level file
- Quadrature.npl, Xilinx project file for ISE/Webpack
- Quadrature.ucf, optional constraints file for pin assignment