RTF Simple UART Core with BAUD Generator
Details
Category: Communication Controller
Created: September 12, 2011
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Beta
Additional info: Design done, FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: BSD
Description
This is a simple uart core which includes a baud generator. The core uses a fixed format: 1 start,8 data, 1 stop bit.
+ baudX8/X16 mode selects in runtime
