RXAUI Interface and RXAUI Interface Adapter

RXAUI Interface and RXAUI Interface Adapter

Details

Category: Communication Controller

Created: March 31, 2009

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: ASIC proven, Design done, FPGA proven, Specification done

WishBone compliant: No

WishBone version: n/a

License: n/a

Description

Overview

RXAUI interface uses two 6.25Gbps SERDES lanes to carry 10GE, instead of using four 3.125Gbps SERDES lanes.
This enables a high port count lower power multi 10GE SOCs.

This projects provides the specifications of RXAUI interface and the verilog code for an adapter from
a XAUI to RXAUI interface