SPIxIF FIFO Buffer Transmit Receive Data

This project provides a full function SPI master interface. It provides for a FIFO buffered transmit and receive data path. Further, a ninth bit in the transmit data controls whether the SPI input data (MISO) is saved into the receive FIFO. This allows this SPI interface module to easily support serial memory devices, whose outputs during command and address loads are undefined, and devices like serial ADCs, whose output data is valid on each transfer cycle. In addition, the module automatically asserts and deasserts the slave select line. Slave select is asserted when data is written to the output FIFO/register, and slave select is deasserted when there's no more data in the transmit FIFO.

A built-in clock generator supports clock rates of 1/2 of the system clock down to 1/256 of the system clock. The shift direction is programmable. This SPI master module also supports all four SPI operating modes. A change-of-state detector is included to automatically change the control signals (mode, clock rate, and shift direction) between transfer cycles.

A limitation of the module is that one system clock cycle is required to change the mode, shift direction, and baud rate selections. Once a transfer cycle begins, the master can change these values but their effect will not take place until one cycle after the de-assertion of slave select, i.e. the end of the current SPI transfer cycle.

This module has been used in a Xilinx XC3S50A-4VQ100I FPGA which implemented a system-on-chip using this module, the P16C5x processor core, and several other modules found here at opencores.org: M16C5x, SSP_Slv, SSP_UART, and DPSFmnCE.

Synthesis/PAR

The following tables define the synthesis and PAR results for the SPIxIF SPI Master Interface module. It is not intended to be used as a stand-alone implementation, but as a peripheral function for soft processor or system-on-chip solutions.

 

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Module	Partition	Slices	Slice Reg	LUTs	LUTRAM	BRAM	MULT18X18	BUFG	DCM
[-] SPIxIF		68/68	40/40	103/103	0/0	0/0	0/0	1/1	0/0

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Met	Constraint	Check	Worst Case Slack	Best Case Achievable	Timing Errors	Timing Score
Yes	TS_Clk = PERIOD TIMEGRP "Clk" 5.200 ns HIGH 50%	SETUP/HOLD	0.020ns/1.231ns	5.180ns	0/0	0/0

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, Synthesis/PAR Results - XC3S50A-4VQ100I FPGA

 

Attribute	Used	Avail	%
Number of Slice Flip Flops	50	1408	2%
Number of 4 input LUTs	103	1408	7%
Number of occupied Slices	68	704	9%
Number of Slices related logic	68	68	100%
Number of Slices unrelated logic	0	68	0%
Total Number of 4 input LUTs	103	1408	7%
Number used as logic	103
Number used as a route-thru	0
Number used as Shift registers	0
Number of bonded IOBs
Number of bonded pads	32	68	47%
IOB Flip Flops	32
Number of BUFGMUXs	1	24	4%
Number of DCMs	0	2	0%
Number of RAMB16BWEs	0	3	0%