UART Block Core with Wishbone Slave Interface
Details
Category: Communication Controller
Created: April 20, 2012
Updated: January 27, 2020
Language: VHDL
Other project properties
Additional info: FPGA proven, Specification done
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
Simple uart core with wishbone slave interface and programmable baud rate generator, based on clock speed and desired baud rate
