UDP/IP Core for PC-FPGA Communication
Details
Category: Communication Controller
Created: December 30, 2015
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: BSD
Description
VHDL implementation of a UDP/IP core! Area-optimized for direct PC-FPGA communication!
An advanced/versatile version of the core is included in the PC-FPGA Communication Platform project!
