AES Encryption All Keylength

AES Encryption All Keylength

Details

Category: Crypto Core

Created: June 24, 2013

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: BSD

Description

Four stage pipeline design working at 361.890MHz on Xilinx's 28nm Kintex 7 speed grade 3 FPGA device. Calculating 4 blocks parallely, encrypting up to 4.25 Gbits data per second (0.361Ghz* 4 stage pipe * 128 bits parallel / 44 cycles a block).