Pipelined FFT/IFFT 64 Points Processor

Pipelined FFT/IFFT 64 Points Processor


Category: DSP Core

Created: January 05, 2010

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: LGPL


Pipelined FFT/IFFT 64 points IP core is a unit to perform the Fast Fourier Transform (FFT). It performs one dimensional 64 – complex point FFT. The data and coefficient widths are adjustable in the range 8 to 16.

Main Features:

  • 64 -point radix-8 FFT.
  • Forward and inverse FFT.
  • Pipelined mode operation, each result is outputted in one clock cycle, the latent delay from input to output is equal to 163 clock cycles, simultaneous loading/downloading supported.
  • Input data, output data, and coefficient widths are parametrizable in range 8 to 16
  • Two and three data buffers are selected.
  • FFT for 10 bit data and coefficient width is calculated on Xilinx XC4SX25-12 FPGA at 250 MHz clock cycle, and on Xilinx XC5SX25-12 FPGA at 300 MHz clock cycle, respectively.
  • FFT unit for 10 bit data and coefficients, and 2 data buffers occupies 1513 CLB slices, 4 DSP48 blocks, and 2,5 kbit of RAM in Xilinx XC4SX25 FPGA, and 700 CLB slices 4 DSP48E blocks, and 2,5 kbit of RAM in Xilinx XC5SX25 FPGA, data buffers are implemented on the distributed RAM.
  • Overflow detectors of intermediate and resulting data are present.
  • Two normalizing shifter stages provide the optimum data magnitude bandwidth.
  • Structure can be configured in Xilinx, Altera, Actel, Lattice FPGA devices, and ASIC.
  • Can be used in OFDM modems, software defined radio, multichannel coding.

,Unicore Systems, http://unicore.co.ua. , link ,