Wishbone FLASH Interface For Parallel FLASH

Wishbone FLASH Interface For Parallel FLASH Click to expand image

Details

Category: Memory Core

Created: June 03, 2008

Updated: November 19, 2019

Language: Verilog

Other project properties

Development Status: Stable

Additional info: Design done, FPGA proven

WishBone compliant: Yes

WishBone version: n/a

License: LGPL

Description

Wishbone to Parallel FLASH interface with integral wait-state generator. This design has been used with the Intel StrataFlash Xilinx Spartan 3E Starter Kit. Provides an 8-bit data interface to the FLASH, and a 32-bit Wishbone Slave Interface with byte enables.

The StrataFlash on the S3E Starter Kit can be programmed using the PicoBlaze RS-232 StrataFlash™ Programmer downloadable from the following site:

http://www.xilinx.com/products/boards/s3estarterreference_designs.htm

Features

- Compatible with Intel StrataFlash J3 on Xilinx Spartan 3E Starter Kit
- Supports byte-mode operation.
- 32-bit Wishbone Slave Interface

Status

- Tested on Xilinx Spartan 3E Starter Kit