Lightweight 8051 Open Source MCS51 Compatible CPU Core
Details
Category: Processor
Created: November 23, 2012
Updated: January 27, 2020
Language: VHDL
Other project properties
Development Status: Beta
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Yet another free 8051 FPGA core.
This is a 6-clocker-equivalent implementation of the MCS51 architecture, aiming at area performance.
A full description of the core features can be found in the datasheet.
Though the core has already executed a Dhrystone benchmark in actual hardware (see below), it is still immature for actual use. A comprehensive test bench has yet to be developed, for starters.
Performance
Synthesis
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| Device | Synthesis Options | Clock Rate | CPU | Timer | UART | Total |
| Altera Cyclone-2 (-C7) | Balanced | 62 MHz | 997 LEs + 29M4Ks + 1MUL9 | 85 LEs | 147 LEs | 1349 LEs + 29M4Ks + 1MUL9 |
| Xilinx Spartan-3A (-4) | Balanced | 35 MHz | 1162 LUTs + 10BRAMs + 1MUL18 | 66 LUTs | 99 LUTs | 1424 LUTs + 10BRAMs + 1MUL18 |
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Benchmark Results
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,adapted for MCUs by ECROS Technology,SDCC,
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| Dhrystone 2.1 Benchmark Results | |
| 1646 | Dhrystones per second @ 50MHz |
| 0.9368 | Dhrystone MIPS |
| 0.0187 | Dhrystone MIPS per MHZ |
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,Dhrystone MIPS,
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,this description of one of CAST's single-clocker 8051s,
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Status
The core has been tried on two development boards for which support files are included (a top entity, pin constraints file and a project file).
The project files are set up to use the Dhrystone demo object code to initialize the XCODE ROM so that they can be tried without installing SDCC or any MCS51 toolchain.
They can easily be used with any other program by using the appropriate package, as explained in the datasheet.
The supported boards are Terasic's DE-1 board for Cyclone-II and Avnet's Spartan-3A Evaluation Kit (an old board for which no link is available).
In short, this is the current status of the project:
| 1. | - Design and implementation finished. |
| 2. | - Already tried on real hardware (Dhrystone demo on Cyclone-2 and Spartan-3A FPGAs). |
| 3. | - No documentation other than this page, a 'quickstart' file and a draft of the datasheet. |
| 4. | - Has not yet passed a rigorous test bench (so no test coverage info is available). |
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Updates
,Rev. 26,
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