MB-Lite Microprocessor - Implementation of Microblaze Instruction Set

MB-Lite Microprocessor - Implementation of Microblaze Instruction Set


Category: Processor

Created: June 19, 2009

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: ASIC proven, Design done, FPGA proven, Specification done

WishBone compliant: Yes

WishBone version: n/a

License: LGPL



The MB-Lite microprocessor is a ligth-weight implementation of the Microblaze Instruction Set Architecture. It is instruction and cycle compatible with the Microblaze EDK 10.1i. It is successfully tested on older and newer Xilinx platforms (EDK 9 and 11). The design has been successfully synthesized for an Altera board as well to show platform independence.


MB-Lite is a highly modular design and is therefore very simple to understand and modify. Features of the MicroBlaze architecture and MB-Lite implementation are:

  • 32-bit data- and instruction bus
  • Harvard architecture
  • Five pipeline stages
  • Cycle as well as instruction compatible with the MicroBlaze Instruction Set Architecture
  • Optional interrupt support
  • Optional wishbone bus
  • Optional multiplier
  • Optional barrel shifter

The following instructions are currently not implemented. All of these instructions are not used by the compiler (mb-gcc) or can be replaced by software libraries.

  • IDIV, IDIVU (Integer Division)
  • TN* (Fast Simplex Link instructions)
  • F* (Floating point instructions)
  • PCM* (Pattern Compare)
  • WIC, WDC (Cache instructions)
  • MTS, MFS, MSR* (Special purpose register instructions)
  • RTBD, RTED (Return from break / exception)

Included design examples

  • Integer unit directly connected to instruction- and datamemory
  • Integer unit with wishbone bus wrapper
  • Integer unit with address decoder
  • Integer unit with address decoder and wishbone bus adapter
  • SOC for synthesis purposes


The core is designed using the two-process design methodology of Jiri Gaisler. All modules use inferred components, the design is not targeted specificly to any platform. However, currently it is only tested on a Xilinx Spartan 3 FPGA. All memory blocks and registers will synthesize to BRAM on xilinx devices.


The organization of the hardware corresponds closely to the implementation of the classic RISC pipeline of Hennesy & Patterson (Computer Organization and Design: The Hardware/Software Approach).