PCI Slave To WB Master

PCI Slave To WB Master Click to expand image


Category: System controller

Created: November 09, 2011

Updated: November 19, 2019

Language: VHDL

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: LGPL


This core implements a 16 MB DWord-addressable memory image in the Wishbone bus (so WB width is 32 bit). Its functionality is reduced to the minimum which is required by the PCI specification (and I'm really trying to stick exactly to the specs).
The whole source code is contained in one file, that makes it easy to implement into a project.
It's not officially WB compatible because master arbitration is not supported.
The biggest differences to pci_mini are:
• Generally more direct and faster accesses. Reads are not delayed, but are completed in the same cycle. After finishing a PCI cycle, a next cycle could begin immediately, no additional wait time is required.
• PCI Byte Enable bits are payed regard to when reading or writing to config registers (but not when accessing memory).
• Interrupts are not supported anymore. It would be easier to connect interrupts from WB directly to the other device instead of routing it through the PCI interface.
• More comments in the code body. My goal was that everyone should be able to understand what's going on (and eventually to change the core to his own needs).

More detailed information is given in the code file.


Finally! I was able to upload the file. The documentation is useless for beginners like me... 😊

Generally, the core is work in progress.
At the moment, I can work with it in my project, but there are some bugs in special cases, e.g. access at an address that doesn't belong to a WB slave etc.

Feel free to write me when you notice a mandatory PCI spec detail I haven't implemented (which is the part I'm most worried about)!