Simple AXI4-Lite bridges for IPbus and Wishbone

Simple AXI4-Lite bridges for IPbus and Wishbone


Category: System on Chip

Created: May 15, 2016

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Alpha

WishBone compliant: No

WishBone version: n/a

License: Others


This project provides very simple bridges from AXI4-Lite interface to IPbus and Wishbone buses.
The design has been tested on Xilinx Zynq (Z-Turn board with xc7z020 chip) and Altera Cyclone V (DE0 NANO SoC board with 5CSEMA4U23C6).

The complete demo designs based on those bridges for Z-Turn board, together with scripts for building the Vivado project may be found at in version_2 directory.

Implementation of Wishbone bridge is very limited. Currently it supports only "Classic Standard" mode.

The project is licensed under Creative Commons CC0 license or as PUBLIC DOMAIN (whatever is better suited for you).