Wishbone to I2C Controller Wrapper

Wishbone to I2C Controller Wrapper


Category: System on Chip

Created: November 03, 2008

Updated: January 27, 2020

Language: VHDL

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: Yes

WishBone version: n/a

License: LGPL


Short: virtually convert an I2C slave into a WISHBONE slave

This is a wrapper for the I2C controller core by Richard Herveille (http://opencores.orgproject,i2c) which transparently converts a WISHBONE transaction into an I2C operation.

Example: a WB read/write of the WB address 09h of this core would schedule and execute the (long) list of commands needed to make an I2C read/write of reg 09h of an I2C device connected to the I2C controller core in OpenCores, and return the result transparently into the WB bus.

IMPORTANT: The current wrapper is for 16 bits I2C slaves, that is I2C reads and writes are composed of two bytes.


- WISHBONE wrapper for the "I2C controller core" by Richard Herveille
- Fully transparent I2C WISHBONE operation
- A WB read/write of address X becomes an I2C read/write of reg. X and the I2C slave's response is sent back to the WB bus.
- Designed for 16 bits I2C slaves
- FPGA proven and works perfect (if you run into problems: take into account this I2C controller's bug solution: http://www.opencores.org/ptracker.cgi/view/i2c370 )
- Limitations: the I2C slave's address is fixed, so that it may be used to control only one slave (can be overriden with minor modifications).


- 03/11/2008: Project created on OpenCores