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LinkedinWISHBONE Protocol to AHB Protocol Bridge
Details
Category: System on Chip
Created: Aug 06, 2007
Updated: Jan 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
Additional info: FPGA proven
WishBone compliant: Yes
WishBone version: n/a
License: n/a
Description
Features
- AHB 2.0 compliant
- Wishbone B.3 compliant
- WISHBONE Burst NOT SUPPORTED
- Fully synthesisable
- Synchronous
- Verilog RTL
- Includes a Verilog Testbench with 9 Testcases
Status
- RTL : Complete
- Testbench : Complete
- Document : Complete
