High Speed Adder Computation for High Performance

High Speed Adder Computation for High Performance


Category: Uncategorized

Created: February 08, 2005

Updated: January 27, 2020

Other project properties

Development Status: Stable

WishBone compliant: No

WishBone version: n/a

License: n/a


To design a large bit adder computation for high performance

When we design an adder for a x bit size, for example 16 bits, a certain delay is required for the adder to perform the computation.

When we increase the bit size to 32 bits, the delay of the adder increases by a factor that is comparable to the doubling effect of the bit size. This increase is because a lot more logic is required to build the 32 bits adder and therefore the critical path is much longer for the 32 bits adder compared to the 16 bits adder.

Similarly when we double the bit size to 64 bits, 128 bits or beyond, the delay for the adder increases. As such, adders with large bit size computation such as 128 bit adder and 256 bit adders are extremly slow.

The objective of this project is to design an architecture for a large bit size adder (128 bits and beyond) that can be used to create an adder than is more efficient in computation, compared to conventional adding methods.

Features required for the adder

- performance critical
The adder must be able to perform computation of large bit size (128 bits and beyond) at a more efficent rate compared to conventional high speed adders.

- design based on standard cell
The adder must be designed using std cell (synthesizable RTL) such that the adder can be easily ported to other process technology. As such performance of the adder may vary due to different std cell libraries, but the objective remains the same: the adder must be higher speed compared to conventional adder for large bit size computation.

- architecture must be modular to allow easy expansion
The adder's architecture must be modular in nature so as to allow easy expansion to larger bit size and not only limited to 128 bits.


- status as of Feb 5 2005
Adder's architecture finalised

- status as of Feb 11 2005
Adder's design on-going using verilog RTL

- status as of March 17 2005
Verified architecture on behavioral coding for 64/128/256 bits
currently writing the synthesizable RTL code

- status as of April 30 2005
Implemented, simulated and tested the synthesizable RTL code for 64/128 bits. Currently implementing and verifying the RTL code for 256 bits using the same architecture