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Details
Category: Uncategorized
Created: Mar 29, 2018
Updated: Nov 19, 2019
Language: VHDL
Other project properties
Development Status: Stable
Additional info: Design done, FPGA proven, Specification done
WishBone compliant: No
WishBone version: n/a
License: Others
Description
VHDL implementation of the 6530 RRIOT (ROM-RAM-I/O-TIMER)
,
- ROM (1024 x 8)
- RAM (64 x 8)
- Two parallel I/O ports
- Timer functions
- Interrupt capabilities
Signal interface
,
,phi2,
,rst_n,
,irq_n,
,rw_n,
,
,cs,
,add[3..0],
,
,din[7..0],
,dout[7..0],
,
,pa_in[7..0],
,pa_out[7..0],
,pb_in[7..0],
,pb_out[7..0],
,
Tests and validation
,
,
,
Registers
Note that, as the R6530 has no edge-detection feature, the address bus has only 4 lines (instead of 5 for R6532).Refer to the original documentation of this chip for registers description.
The only difference is that this implementation use a single cs signal for selection. No need of CS1, CS2, RS0, nor A4..A9, as the RAM/ROM are not implemented.
