Optimized SDRAM controller
Details
Category: Uncategorized
Created: October 04, 2006
Updated: January 27, 2020
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: n/a
Description
This SDRAM controller is optimised for speed. It works efficiently at frequencies higher than 100 Mhz. It's been tested on Altera devices and appears to be completely SOPC Builder Avalon compatible.
Features
- Optimised for speed;
- Altera Avalon compatible;
- Init pause and refresh period can be changed inside the source file;
- all others times are fixed to cycles (see src comments);
- Configurable bank, row, column widths and clk frequency.
Status
- tested
- used in real hardware designes