SystemC/Verilog Random Number Generator

SystemC/Verilog Random Number Generator


Category: Uncategorized

Created: August 19, 2004

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: LGPL


A SystemC/Verilog random number generator based on the combination of a LFSR and a CASR with very good statistical properties. Based on the Thomas E. Tkacik at CHES 2002 work. For more information in spanish visit


- Very good statisticall properties
- Synthesizable


- Done