Real Time Clock IP Core with Wishbone Bus Complaint

Real Time Clock IP Core with Wishbone Bus Complaint


Category: Uncategorized

Created: July 07, 2003

Updated: January 27, 2020

Other project properties

Development Status: Planning

WishBone compliant: No

WishBone version: n/a

License: n/a


Real Time Clock IP core with wishbone bus complaint. The RTC can transmit data to CPU as Binary Coded Decimal (BCD) values through wishbone bus. The data include the time by second, minute, hour, date, day, month, and year. It is 24-hour format. The RTC module can work with an external crystal that the frequency is not very fixed, such as 32.768kHz and so on. It also can generate two flexible interrupt requests: alarm and repetitive mode.

IMAGE: structure.jpg

FILE: structure.jpg
DESCRIPTION: Structure of wb_rtc core

IMAGE: ports.jpg

FILE: ports.jpg
DESCRIPTION: Ports of wb_rtc core


- BCD number: second, minute, hour, date, day, month, and year;
- Determine whether the year is leap year;
- Year 2000 problem is removed;
- Either analog crystal oscillator input or digital clock input, and clock input is not fixed;
- Repetitive interrupt mode, Programmed to provide 6 different interval interrupt requests: once per second, once per minute, once per hour, once a day, once a week, once a month;
- Alarm interrupt mode, Programmed to generate interrupt request signal when real time clock equals to the time stored beforehand in the register;
- Written in verilog, and fully synthesisable.


Verilog RTL code and simulation is finished and available.
It was verified in an Altera APEX EP20K400E SOPC development board.