Highly Customizable Wishbone Monitor Controller

Highly Customizable Wishbone Monitor Controller


Category: Video Controller

Created: September 25, 2001

Updated: January 27, 2020

Other project properties

Development Status: Beta

WishBone compliant: Yes

WishBone version: n/a

License: n/a


Wishbone Monitor Controller is a set of freely available VHDL cores. It contains a central building block containing the basic functionality. It can then be sorrounded by various helper functions to add functionality. The central core comprises of a sync generator, a pixel data generator, a memory interface and a CPU interface. It is specificly designed for slow 8-bit systems (although CPU interface size can be set) with no high needs about a display. It is also designed to be simple and small (cheap). The target is the whole design to be well fit in an Altera ACEX 1k30 device which is available for around 10USD.

Individual module decriptions

Building blocks


For a fast breafing here are the main design goals and features of the various modules:

- Highly customizable sync generation with polarity control
- Capable of driving EGA/VGA/Hercules/CGA monitors
- Multi-scan support for low resolution modes
- Internal memory for multi-scan, for even less memory accesses
- FIFO de-coupled memory interface and pixel output circuit
- Wisbone pixel memory interface
- 16-bit pixel memory support (later parametrizable)
- Programmable color depth (1,2,4,8 bits per pixel)
- ~80Mhz pixel clock (wish)
- Standard parametrizable Wishbone CPU bus interface
- Syncron internal structure
- Fully synthesizable (using Leonardo Spectrum)
- Palette support (3x5 bits plus key bit in each entry)
- Accelerator functions for common display operations
- Mouse cursor support if it fits to the chip (wish)


- Central core implemented
- Palette and Accelerator implemented
- Cores compile under ActiveHDL and Leonardo Spectrum
- Cores simulate well (some more validation still needed)
- All functionality fits into a 1k30 chip
- Synthesized central core works as expected but max. clock rate is ~60MHz
- When all function synthesized max. clock rate is ~35MHz :-(((


- More simulation to proove all core functionality
- Port to other (Xilinx Spartan-II) FPGA architectures
- Optimize design to encrease clock speed
- Implement Mouse sprite block
- More sample applications (complete designs)
- Sample programs
- Parametrizable pixel memory interface
- Generic version for fixed configuration (even much smaller)
- LCD support (??)
- high-color support (??)
- Develop a target board and try the core in real