As 5G Begins and Moore’s Law Ends, Multichip Packaging May Be a Memory Solution

October 26, 2020 by Dr. Steve Arar

As 5G speed and storage demands collide with the end of Moore's law, chipmakers are turning to multichip packaging to save space and power.

5G technology is expected to provide wireless communications with less than 1 ms latency and a throughput up to 50 times faster than existing 4G networks.

This speed will lay the foundation for incredible multimedia and video experiences. However, taking full advantage of these capabilities requires a high-performance memory system that can keep up with the 5G speed and storage requirements. 


5G Requires High-Performance Volatile and Non-Volatile Memories 

To make the blazing-fast downloads of 5G a reality, we need a high-capacity, fast storage device. As an example, consider streaming UHD content. In this case, our mobile device will need to temporarily buffer the video in the background.

This requires a large memory with read/write operations as fast as the network. The figure below illustrates that 2D planar NAND flash cannot meet the needs of today’s wireless communications. 


The growth of mobile device write speed in tandem with network speed

The growth of mobile device write speed in tandem with network speed. Image used courtesy of Micron (PDF) 


One short-term solution to overcome the flash storage bottleneck can be 3D NAND technology where layers of storage dies are stacked to increase memory capacity and performance.

High-performance flash storage is only half the 5G memory challenge. Even LPDDR4-based chipsets will be pushed to their limits with the vast volume of data that a 5G device should process. Without an improved RAM memory, we’ll have lower video resolution, frustrating lags, and limited features.


What is a Multichip Package?

As we reach the end of Moore’s law, we need to rely on other techniques to improve the performance of our electronic systems. One of these techniques might be multichip packaging, which places different chips in a stacked fashion inside the same package. One recent example of this packaging technique is Samsung's 3D IC technology.

The following figure shows a stacked product with three different dies glued one on top of the other. 


Example of a multichip package

Example of a multichip package. Image used courtesy of Rino Micheloni


Note how bonding wires connect the IOs of each of these dies to the package substrate. 

Multichip package (MCP) allows us to have different memory types—for example, non-volatile flash and volatile DRAM—inside the same chip. The MCP technology can enable high-density, cost-effective memory solutions with improved performance at a lower power usage.

Besides, MCPs can simplify the design process by offloading the embedded memory of the system MCU. In terms of power efficiency, it is possible to remove the power to an inactive die of the MCP while the other dies in the package are operating. This feature enables new low-power sleep modes. 

In general, the non-volatile memory of an MCP memory is used for boot-up of applications, operating systems, and other critical code execution. The volatile memory serves as high-speed temporary memory.


Micron’s New Multichip DDR5 Package, the uMCP5

Micron has recently announced a new MCP memory, uMCP5, that integrates a low-power DDR5 (LPDDR5) RAM with the latest generations of universal flash storage (UFS) into a single package. This memory is specifically designed for next-generation 5G devices. Micron claims that the uMCP5 can save up to 55% of a PCB's area compared to a discrete solution that uses stand-alone LPDDR5 and UFS chips.


Low Power Consumption

In a previous article, we discussed that future 5G systems will be highly complex, probably employing massive MIMO with hundreds of antenna elements. With such power-hungry systems, thermal management is a major issue and we need to keep the power consumption of different building blocks to a minimum.


Depiction of the new uMCP5

Depiction of the new uMCP5. Image used courtesy of Micron

The LPDDR5 memory employed in the new product consumes 20% less power compared to a Micron LPDDR4 solution. The new device offers UFS 3.1 with about 40% less power consumption compared to a UFS 2.1 product. These power efficiency boosts can extend the battery life of 5G devices.


Lifespan, Speed, and Storage

Micron claims that the uMCP5 can extend the lifespan of future smartphones by providing 66% improvement in the NAND endurance. According to Micron, its NAND memory can be programmed and erased by 5,000 times without degrading the device performance.

With UFS 3.1, the write speed is improved by 20% and the sequential read operations are accelerated by a factor of two compared to a UFS 2.1 product. This can lead to a 20% improvement in download speeds and facilitate 5G capabilities.

The LPDDR5 technology employed in the new product increases the DRAM bandwidth by 50% to about 6,400 Mb/s in comparison to an LPDDR4x product. This enables multitasking of data-intensive applications and paves the way for data-rich features such as higher-quality image processing, virtual reality, immersive gaming, and edge computing.