Arduino Cinque Brings Together RISC-V and the Popular Arduino PlatformMay 29, 2017 by Chantelle Dubois
Open source hardware met open source instruction set architecture this month when SiFive announced the Arduino Cinque—an Arduino development board based off the RISC-V ISA.
Open source hardware met open source instruction set architecture this month when SiFive announced the Arduino Cinque—an Arduino development board based off the RISC-V ISA. This announcement is certainly an indicator that SiFive and the RISC-V foundation are taking their efforts seriously in trying to expand their baseline of users of the ISA.
This is the second RISC-V based development board put out by SiFive, the first being the HiFive1, which held a successful crowdfunding campaign late 2016 and is compatible with the Arduino platform. The HiFive1 retails for $59 on the SiFive website.
So far only prototypes of the Arduino Cinque were available for demonstration at the Maker Faire Bay Area on May 20th, but what is known so far is that the board will be hosted on SiFive’s Freedom E310 customizable SoC, which runs off the E31 CPU Coreplex (32-bit RV32IMAC Core). The Freedom E310 claims to be the fastest microcontroller on the market, capable of running at 320 MHz.
The Arduino Cinque will also have built-in Wi-Fi and Bluetooth capabilities with the inclusion of an efficient, low-power Espressif ESP32 Wi-Fi/Bluetooth hybrid chip.
Image courtesy of LinuxGizmodos.
Freedom E310 Specifications
- E310 CPU Coreplex (32-bit RV32IMAC core)
- 320 MHz operating speed
- 16KB L1 Instruction Cache
- 16KB Data SRAM Scratchpad
- Hardware multiply/divide
- Debugging module
- One-time programmable non-volatile memory (OTP)
- On-chip oscillators and PLLS
- UART, QSPI, PWM, and timer peripherals
- Low-power standby mode
SiFive's Freedom E310 Chip. Image courtesy of SiFive.
- RV32I Base Integer Instruction Set, Version 2.0
- “M” Standard Extension for Integer Multiplication and Division, Version 2.0
- “A” Standard Extension for Atomic Instructions, Version 2.0
- “C” Standard Extension for Compressed Instructions, Version 1.9
- RISC-V Privileged ISA Specification, Version 1.9.1
- RISC-V External Debug Support, Version 0.11
Espressif ESP32 Specifications
- 240 MHz dual core Tensilica LX6 micrcontroller
- 520KB SRAM
- 802.11 BGN HT40 Wi-Fi transceiver, baseband, stack, and LWIP
- Classic and BLE integrated dual mode Bluetooth
- 16 MB flash memory
- On-board PCB antenna
- IPEX connector for use with external antenna
- Ultra-low noise analog amplifier
- Hall sensor
- 32 KHz crystal oscillator
- GPIOs for UART, SPI, I2S, I2C, DAC, and PWM
Espressif ESP32 Chip. Image courtesy of CNX-Software.
RISC-V Visions of the Future
The RISC-V Foundation has been actively working to spread the idea and benefits of the open-source ISA, regularly hosting workshops, participating in conferences, and collaborating with academia and industry.
Early this May, the foundation hosted a four-day workshop in Shanghai China, had the ISA demonstrated on a variety of platforms during Embedded World 2017 in Germany this past March, and the first RISC-V International Conference was held this past April in India.
The RISC-V Foundation has also been working with researchers from Princeton University which identified flaws with the ISA design. The problem occurred in high-performance applications of RISC-V in which memory-ordering rules were being violated. The group presented their findings this past April at the 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems.
The announcement of the Arduino Cinque occurred the day before a panel discussion titled “Manufacturing Your Own Chips: Is Open Source (like RISC-V) Making it Easier?” at the Maker Faire Bay Area, which featured the man who coined the term “RISC”, David Patterson.
The challenges of RISC-V, some of its history, and who its competitors are can be found in this March All About Circuits Article: Is 2017 the Year that RISC-V Will Catch on?
Feature image courtesy of LinuxGizmodos.