Cars, Control, and Communication: A Product Roundup From Embedded World

April 16, 2024 by Duane Benson

Embedded World 2024 lived up to its promise of delivering exciting semiconductor news. Here are four bits that caught our eye for automotive, RISC-V, Bluetooth LE, and AI applications.

Embedded World 2024 explored the many ways computing systems and wireless connectivity are advancing across industries, with automotive being one of the most highlighted at the event. 


Brian Carlson

Brian Carlson, NXP's global marketing director, at Embedded World 2024 in Nuremberg, Germany.


With electronics now accounting for about 40% of a car's cost (with this figure expected to reach 50% by 2030), it’s no surprise that our first two announcements from NXP and Infineon target the automotive electronics market. The latter two announcements from this show floor roundup examine RISC-V as an up-and-coming competitor to Arm and edge AI in a Bluetooth chip—perhaps one of the least expected places for native AI processing.


NXP Releases 'Super-Integrated' Processor for Vehicle Control

NXP announced the first member of its new S32N vehicle processors. The S32N55 is designed to integrate multiple engine control units (ECU) into one software-defined vehicle (SDV) system. The S32N55 enables designers to dynamically configure hardware isolation for critical functions traditionally controlled in separate ECUs. This separation of functions into discrete ECUs maintains adequate system isolation. You can’t have a bug in the infotainment system bringing down the engine fuel control.

The vast number of automotive systems needing electronic control has led to abundant discrete ECUs in today’s cars. More ECUs require more space and more power—and entail more potential points of failure. The NXP S32N family of vehicle processors is designed to mitigate this problem by integrating multiple ECU functions into one processing unit, called super-integration. 


S32N55 block diagram

S32N55 block diagram. Image used courtesy of NXP Semiconductors (Click to enlarge.) 

The family is powered by 16 real-time split-lock Arm Cortex-R52 cores, running at 1.2 GHz. The chip can support compliance with ISO 26262 ASIL-D safety levels by operating in either split or lockstep modes, allowing for super-integration without compromising safety. It also contains two Cortex-M7 cores for overall system operations and communications. It has 49 MB of tightly integrated SRAM and can be expanded with LPDDR4X/5/5X DRAM, LPDDR4X Flash, and NAND/NOR Flash memory. It communicates with the outside world via a time-sensitive networking (TSN) 2.5 Gbit/s Ethernet switch, CAN hub, four CAN XL interfaces, and a Gen 4 PCI Express interface, and is capable of over-the-air (OTA) upgradability.

The S32N processor family fits into NXP’s Open S32 CoreRide Platform. CoreRide is a development platform that customizes automotive electronics in software. NXP refers to this as a software-defined vehicle (SDV) system. CoreRide, with the S32N processors, allows one set of hardware to be configured in multiple ways to support different types of vehicles and different combinations of infotainment, navigation, climate control, and system control.


Infineon Debuts Programmable, High-Voltage SoC Family 

Infineon’s new high-voltage, mixed-signal (HVMS) programmable system-on-chip (PSoC) family tackles the problem of combining ever more control functionality into smaller spaces. The highly-integrated PSoC microcontroller chips target touch-enabled HMI and other smart sensing automotive applications.

Infineon designed the 32-bit PSoC 4 HVMS Arm Cortex-M0+ as a one-chip solution for smart sensors. It integrates a Cortex M0+ MCU, connectivity, and an analog front-end. It packs programmable digital and analog building blocks and automotive communications blocks into a highly configurable chip. It is high-voltage (12 V) compatible for easier automotive applications and meets automotive safety level ASIL-B.


The 32-bit PSoC automotive high-voltage Arm Cortex-M0+ portfolio

The 32-bit PSoC automotive high-voltage Arm Cortex-M0+ portfolio. Image used courtesy of Infineon

Some of the other key specs of the family include: 

  • AEC-Q100 qualification and small QFN packages with wettable flanks
  • ISO26262 ASIL-B compliance for safe operation at temperatures up to 125°C
  • Arm Cortex-M0+ processor with up to 128 KB of embedded Flash and 16 KB of SRAM
  • Fifth-generation Capsense technology with eight times better SNR than the previous generation
  • 12-bit SAR ADC, up to two operational amplifiers, and low-power comparators

The software development stack contains robust support for several key automotive system functionalities. It comes with library support for the automotive peripheral driver library (AutoPDL), the automotive middleware library for Capsense, and the safety library (SafeTlib) for automotive PDL. The stack is compliant with key industry automotive software standards such as ASPICE, MISRA2012 AMD1, and CERTC.

Infineon PSoC chips have proven versatile in a wide variety of embedded applications. By adding 12-V I/O, support for key automotive standards, and a robust automotive development chain and library set, the PSoC 4 HVMS brings the PSoC configurable mixed-signal capability to automotive developers.


The 'Highest-Performance RISC-V Dev Board' on the Market

Also announced at Embedded World 2024 was the HiFive Premier P550 development board from SiFive. The new RISC-V board, promoted as the highest-performing RISC-V development board, is a development environment for SiFive’s Performance P550 processor, which features out-of-order processing in a RISC-V architecture.  

Out-of-order processors split instructions into three steps: instruction fetch, instruction dispatch, and instruction queue. Instructions wait in the queue until their operands are available, at which time they are sent to the appropriate processor section to be operated upon. This means that if the input is ready, an instruction may be operated on prior to other instructions that have been in the queue longer. This speeds up program execution by not waiting for non-dependent prior operations.


HiFive Premier P550 development board

HiFive Premier P550 development board. Image used courtesy of SiFive

The quad-core P550 processor integrates this capability into SiFive’s RISC-V IP, and the new development board makes the processor available to developers now. The board runs Ubuntu and is designed with a system-on-module (SoM) architecture for flexible implementation and upgrading.

Key features of the P550 processor include:

  • Quad-core SiFive Performance P550 64-bit RISC-V processor
  • Three-issue out-of-order capability
  • 256 KB L2 cache and 4 MB L3 cache
  • 2D/3D GPU, hardware video encoder/decoder
  • NPU, DSP, and MIPI DSI 
  • Integrated high-speed DDR5 memory controller
  • Root complex PCI Express Gen 3 x4

The development board comes with 6 GB of 64-bit LPDDR5-6400 memory, 128 GB of eMMC memory for fast boot, PCI Express Gen3 x4 (1 PCIe x16 slot), 5x USB 3 ports, the Ubuntu OS,  and Freedom U-SDK.


Alif Claims First BLE/Matter MCU With Native AI Processing

Alif Semiconductor announced the "world’s first BLE and Matter wireless microcontroller" to feature neural co-processors for AI/ML workloads. The BLE 5.3 chips, called the Balletto family, target home automation and Matter protocol systems. Matter is a universal protocol that supports wireless home automation devices from multiple manufacturers.


Balletto family

The ultra-low-power BLE MCU. Image used courtesy of Alif Semiconductor

Home automation contains a mix of line voltage, battery, or solar-powered devices. In many applications, size is limited. Alif added native AI processing to this device while keeping size and power draw low. The Balletto family of BLE MCUs selectively powers off-chip sections when unused to maintain ultra-low power consumption. 

Native AI may seem excessive for small, low-power devices, but it is becoming increasingly important for critical decision-making. To this end, the chip is powered by an Arm Cortex-M55 CPU and an Arm Ethos-U55 neural processing unit (NPU). The NPU, backed by tightly coupled memory (TCM), can perform up to 46 GOP/s. It extends the audio capabilities with hardware-accelerated AI/ML models.

The neural processor performs 15x better than a non-neural Cortex-M4. It has an analog front-end with high-precision ADCs, including a 24-bit sigma-delta, DAC, an Octal SPI interface, and up to 77 GPIO. Versions can have up to 2 MB of high-speed MRAM and 2 MB of zero-wait state SRAM.

The Balletto processors share architecture with Alif’s Ensemble family, so developers familiar with one family can easily move to the other.


More Performance in More Arenas

Strong gains in performance and efficiency are not limited to massive server farms. These four new devices show that the march of performance, optimization, and AI is on its way everywhere.



Catch Up on More Embedded World News

Renesas Rolls Out Entry-Level MCU With ‘Best-in-Class’ Power Consumption

NXP Launches Scalable Wireless MCU Series at Embedded World

AMD Announces Two New Adaptive SoCs for Faster Edge AI

Altera Infuses AI Into New Mid-Range FPGAs

Arm Shows Off New NPU and IoT Reference Design at Embedded World