Recently, Flex Logix announced that co-founder Cheng Wang received three patents for his streamlined embedded FPGA (eFPGA) designs. Wang’s eFPGAs designs in new process nodes take less time to manufacture—approximately six months—and sport a density similar to traditional FPGA chips.
According to a press release from Flex Logix, the first patent (US Patent 9,817,933) was issued to Wang and Flex Logix co-founder Dejan Markovic for the five FPGA interconnect designs they invented at UCLA. They featured this interconnect in a paper that received the 2014 International Solid-State Circuits Conference’s Outstanding Paper Award. The second and third patents, (US Patents 9,503,092 and 9,793,898), were issued to Wang for his and Flex Logix’s development of the EFLX® eFPGA.
Graph describing the make-up of the patented designs. Image courtesy of Flex Logix
The History of FPGAs and Patents
What do these patents mean for Flex Logix’s long-term development plans? A Berkeley study entitled “Analysis of Xilinx’s Patent Strategies” digs into two central patents in Xilinx’s, repertoire of 33 unique patents. According to the study, “In sum, these two patents cover both a configurable logic element and an efficient means of interconnecting an array of these devices.”
When managing their patents in the 90s, it appears that Xilinx aimed to discourage those who wanted to enter the realm of FPGA development and diminish competition as much as possible. But after years of patent management, Xilinx reached a bit of a mixed result. According to the Berkeley study, lawsuits between Xilinx and competing company Altera “reduce[d] competition by raising the barriers to entry” and slowed technological advances.
Moving Forward with Flex Logix's Patents
While Flex Logix’s own patent management plans have yet to be seen, the company is currently promoting their specialized eFPGA specs online, aiming to draw buyers in with a design that is “twice as area-efficient as traditional FPGA mesh interconnect”.
Diagram differentiating between traditional FPGAs and eFPGAs. Image courtesy of Flex Logix.
As of right now, these interconnect designs are critical to Flex Logix’s eFPGA approach, but other competitors are sticking with their traditional mesh approach. “If they switch to our designs," Geoff Tate, Flex Logix’s CEO and founder, told AAC, "it would be a huge investment, but I don’t see them doing that anytime soon." According to Tate, the other players in the FPGA industry, namely Xilinx and Altera, have too much money already invested in their own designs to switch to “a totally different way to do FPGA interconnect.”
“We think we have the better mousetrap,” Tate says, “but only time will tell.” And if other FPGA companies do decide to switch over to Flex Logix’s interconnect designs, their patents will be set in place.
“There might be a third way to do this, and that’s the great thing about the industry,” Tate says. But for now, Flex Logix is betting on their “mousetrap.”
A Constant Redesign of Interconnect
Flex Logix’s eFPGA designs tout this new interconnect design. “One FPGA company executive once said they don’t really sell programmable logic; they sell programmable interconnect,” Tate writes in an article for SemiEngineering.com. Because most FPGA designs contain up to 80 percent traditional mesh fabric, which transmits signals throughout the FPGA’s logic blocks, these designs must scale with more and more interconnect as the project grows in size and complication. These designs were recently added to SiFive’s DesignShare initiative, a collaboration between companies to assist emerging semiconductor and custom-silicon companies through low- or no-cost IP sharing.
Wang approached Tate at UCLA with a new way to design FPGA interconnect. This process “could cut the FPGA fabric size almost in half,” resulting in more compact designs that use fewer metal layers. This makes it easier for designers to match eFPGAs to their projects, as the chips are compatible with nearly all types of metal stacks. “If we used a large number of metal layers, like FPGA chip companies,” Tate writes, “customers would have to adopt our metal stack OR we’d have to re-route designs, taking time and doing surgery on the GDS.”
This article was updated on 12/19/2017.