Imperas Clears the Haze Around RISC-V Processor Verification
MIPS is tapping Imperas to simplify the process of testing and verifying RISC-V processors. What goes into verification when it comes to RISC-V?
When working with central processing units (CPUs), hardware designers must often hassle with conventional verification methodologies. This process begins by selecting a processor, which is generated and maintained by one owner—making it a single-sourced unit. Others parties can reuse units of logic or an IC design under a licensed shared agreement.
Next, designers must establish a verification plan that shows how the processor will compile software to carry out a system's functionality. This plan requires the user to select tools, tests, test benches, EDA tools and models, and integration testing methods.
The challenges of processor verification. Image used courtesy of Axiomise
As a contrast, RISC-V—an open standard instruction set architecture—gives designers a royalty-free, open-source platform that mitigates the challenges of traditional testing and verification methods, saving time, money, and design effort. Once RISC-V was introduced in 2010, semiconductor developers began aiming to make their next-gen ICs RISC-V compliant.
MIPS, a developer of RISC-based processor architectures and IP cores, recently announced that it has tapped Imperas’ reference model to further simplify the verification and testing of RISC-V-based embedded systems. Imperas is a company that specializes in RISC-V processor models, hardware design verification, and virtual prototypes for EDA.
MIPS and Imperas Launch a New Verification Solution
MIPS claims its RISC-based processor architectures and IP cores allow semiconductor companies to create efficient, scalable, and trusted products for high-end networking equipment.
The company recently announced an extension of its ongoing collaboration with Imperas by adding a new “step-and-compare” verification line to compare the implementation of register-transfer-level (RTL) processors against Imperas’ gold reference model. This model is encapsulated within a SystemVerilog environment.
A step-and-compare flow using Imperas' reference model. Image used courtesy of Imperas
RTLs provide a digital design and verification flow for the overall design. They include crucial registers that withhold state inputs, which control changes from the logic side of the design. Monitoring, controlling, and testing every RTL requires various verification methods to help designers simulate, model, and improve electronic systems. The SystemVerilog environment is a well-known reference for SoC verification that allows designers to navigate through each benchmark in the Verilog programming language.
The Merits of RISC-V Processor Verification
RISC-V processor verification has four key requirements:
- Established RTLs
- Reference model
- Pre-selected tests
- Test and verification plan
MIPS says its RISC-V verification platform provides all of the required tools and tests to generate a design plan for any system.
What slows down designers when they go with conventional RTL-based simulation is testing and processing. By switching to RISC-based simulations, designers can use reference models instead of an RTL to simulate and model during prototyping, which debugs and analyzes throughout each test bench.
RTL and ISS co-simulation flow. Image used courtesy of RISC-V
The designer can also perform a side-by-side configuration for interactive debugging sessions if an issue is found. All simulations are automated, so designers can halt long simulations once an issue is detected. This means users won't have to wait for the remaining benchmarks to be completed.
As CPUs execute their software regime, it's also important to test the architecture to detect bugs and identify how to remove them for a smooth design flow.
A Growing RISC-V Ecosystem
For system on chip (SoC) developers, selecting an appropriate processor IP comes with many requirements, but one key factor is finding a supportive open standard, instruction set architecture (ISA). By choosing RISC-V, MIPS and Imperas are providing developers with unlimited access to EDA tools, instruction set simulators, and system emulators to efficiently address any potential threats or errors for embedded devices.
An upcoming RISC-V Summit will be held in San Francisco, California December 6–8th that will allow designers to view new advancements that will help them navigate more easily through the RISC-V ecosystem.