Keysight Preps for LPDDR6 With Memory Design and Test Options

Keysight Technologies has announced a new complete design and test solution for Low-Power Double Data Rate 6 (LPDDR6) memory systems. The JEDEC standards committee is expected to finalize LPDDR6 in Q2 2025. The Keysight system will be ready in time for designers to use the new standard.

Keysight’s Pedro Merlo and the M8040A system at the 2025 Chips Summit.

The solution includes test automation tools to significantly improve device and system validation operations. The system relies on existing and new hardware and software modules. It is designed to enable complex tests even for those engineers without significant bit error rate test (BERT) experience. One of the key components of the memory test solution is the new M8040A BERT station. The M8040A delivers clean, non-return to zero (NRZ) and pulse amplitude modulation 4 (PAM4) signals at up to 64 GBaud. 

A Basic Overview of the LPDDR6 Test Solution

Keysight's new LPDDR6 test system, the M8040A, is based on the company's UXR oscilloscope and high-performance M8040A Bit Error Ratio Tester. It includes transmitter and receiver test applications and the Advanced Design System (ADS) Memory Designer workflow solution. The test solution pairs with Keysight system development tools, such as its EDA software and W3626B Memory Designer bundle.

W3626B ADS Core Memory design, layout, and test workflow bundle. Image used courtesy of Keysight Technologies

The complete test solution includes specialized de-embedding capabilities to allow direct measurements from BGA-packaged components. It can test against multiple jitter, crosstalk, and noise scenarios and optimize signal integrity with BER analysis and receiver equalization functions.

The M8040A: A Bit Error Rate Tester

Keysight developed the M8040A for R&D and test engineers designing maximum-performance LPDDR6 memory systems. It can test serial I/O ports at up to 32 GBaud and 64 Gbaud. Part of the M8040A’s speed and low noise performance can be attributed to the remote head architecture that supports test cables as short as 1.85 mm.

Keysight's M8040A 63 GBaud BERT. Image used courtesy of Keysight Technologies

Other notable features of the system include: 

• 2 to 64 GBaud PAM4 signal data rates
• Real-time PAM4 true error detection at up to 58 GBaud
• Built-in de-emphasis, analyzer equalization, and clock recovery
• Integrated and calibrated jitter injection: RJ, PJ1, PJ2, SJ, BUJ, and clk/2 jitter
• Two pattern generator channels per module to emulate the aggressor lane
• Interactive link training and SKP OS filtering for 8/16/32/64 GT/s PCI Express

In addition to memory, the M8040A can test input for a wide variety of PAM4 and NRZ data format interconnect standards. Supported data formats include:

• PCIe 6.0/5.0/4.0
• TBT3
• 400 GbE
• 50/100/200/400/800 GbE
• OIF CEI-56G and CEI-112G
• 64 G/112 G Fibre Channel
• Infiniband-HDR
• Proprietary interfaces for chip-to-chip, chip-to-module, backplanes, repeaters, and active optical cables

The Upcoming LPDDR6 Memory Standard

LPDDR6 is the next generation of high-speed, low-power SD RAM. Optimized for mobile devices, LPDDR operates with reduced power draw while still providing high-performance operation. While the JEDEC LPDDR6 standard is not yet finalized, test and validation are required at this point in the standard’s development. Keysight is collaborating with JEDEC to develop and finalize the standard. The new test systems will help with that process and allow system developers to validate their products when LPDDR6 RAM is available.

LPDDR6 is a follow-on to the five-year-old official standard, LPDDR5, and its two extensions, LPDDR5X and LPDDR5T. The new specification is expected to have a 10.667 to 14.400 Gbps data rate and deliver 28.8 to 32 GBps bandwidth, possibly up to 38.4 GBps.

The improvements from LPDDR 5 to LPDDR 6 include higher speeds, a wider data bus, a new channel and sub-channel architecture, and a new burst length of 24 bits, up from LPDDR5’s 15-bit burst length. Test systems must operate as virtual memory controllers and push the in-test system to maximum performance levels or beyond. This includes a physical layer (PHY) with both transmit and receive functionality.

LPDDR6 Support Beyond Mobile

While Keysight designed the new LPDDR6 memory for mobile devices, it is likely to find a home in fixed installations as well. AI machine learning server systems and data centers are power-critical applications, with servers and data centers requiring massive numbers of processors and their accompanying memory blocks.

AI and high-performance computing are a balance between performance and power consumption. LPDDR6 promises to sit in that happy medium between performance and power, and test solutions like Keysight's may support the memory standard's adoption.