NXP Releases Radar SoC Featuring On-Sensor L2/L2+ ADAS Processing

NXP Semiconductors recently announced the SAF8444, a new automotive radar system-on-chip (SoC) for front- and corner-radar applications.

The SAF8444H single-chip radar solution. Image used courtesy of NXP

With an eye on EURO NCAP 2030 standards, NXP designed the SAF8444 as a one-chip solution that fuses camera and radar data to reduce reliance on centralized domain controllers.

The SAF8444

NXP designed the SAF8444 in 28-nm RFCMOS to handle advanced driver assistance systems (ADAS) signal processing entirely on the sensor itself. That processing begins with a four-transmit, four-receive transceiver with up to 4 GHz of effective chirp bandwidth, enough to support short-, medium-, and long-range sensing. In addition, NXP built camera-radar data fusion directly into the SoC, meaning automakers no longer need to drive up design costs and complexity with an external, dedicated fusion processor.

Beyond radar processing, NXP also built the SAF8444 to be a robust solution concerning RF resilience, security, and compliance. For instance, the chip features a dual-threaded radar accelerator that supports interference mitigation, which the company says enables anti-jamming algorithms to execute without displacing core radar detection tasks. For functional safety, the SoC follows the ISO 26262 SEoOC methodology and supports ASIL-B applications through a built-in monitoring circuit. Meanwhile, a hardware security engine (HSE) covers EVITA Full and SHE+ profiles and complies with ISO/SAE 21434 standards, and the chip carries AEC-Q100 Grade 1 qualification.

Block diagram of the SAF8444H. Image used courtesy of NXP

Currently, NXP offers the SAF8444 in two configurations. The SAF8444E variant pairs an Arm Cortex-M7 at 320 MHz with NXP's SPT 3.4 radar signal processor and an integrated BBE32 Vector DSP.  The SAF8444H option adds an Arm Cortex-A53 at 320 MHz and upgrades to SPT 3.5 for heavier perception workloads. Both variants include up to 4 MB of ECC-protected SRAM, dual CAN-FD ports, and SGMII Gigabit Ethernet at 10/100/1000 Mbit/s.

On-Sensor Radar Processing Architecture

Conventional automotive radar sensors are range-Doppler front ends that forward detect target data over a high-speed link to a central processing domain. As ADAS features become more computationally intensive, these sensors need more bandwidth on the vehicle network. The resulting rise in the cost of centralized compute hardware has put pressure on automakers to find more efficient processing architectures.

Moving perception algorithms from the central domain to the sensor is one option that provides improved efficiency. When a radar sensor outputs object-level detections rather than range-Doppler maps, it reduces the volume of data transiting the network backbone and allows system architects to reduce or eliminate dedicated ADAS compute modules. Research into distributed radar processing architectures has shown that this approach can lower overall system power consumption, which is especially important for electric vehicle platforms where power budgets are tightly managed.

Basic scheme of an FMCW radar. Image used courtesy of MDPI

Chirp bandwidth is a major variable in this context. For frequency-modulated continuous wave (FMCW) radar, range resolution scales inversely with bandwidth. A 4-GHz chirp bandwidth, for example, corresponds to a theoretical range resolution of approximately 3.75 cm, enabling finer object discrimination in near-field and parking scenarios. Achieving this bandwidth in a power-efficient design, however, requires tight control over parasitic loading in the signal chain.  

Availability and Development Support

The SAF8444 is currently in pre-production, with development support available to lead customers. NXP backs the platform with a Radar SDK, a safety framework SDK, and HSE firmware with over-the-air update capability. Developers also have access to an evaluation kit using NXP’s S32 Design Studio toolchain, which supports GCC, WindRiver DIAB, and Green Hills compilers.