OpenHW Group Announces Multi-core Evaluation SoC Based on the NXP iMX Platform
The Core-V Chassis evaluation SoC will feature a CV64A 64-bit core and a CV32E 32-bit coprocessor core as well as 3D and 2D GPUs.
At this year’s RISC-V Summit held in San Jose, California, the OpenHW Group announced plans to release a Linux-powered Core-V Chassis multicore evaluation SoC. The SoC will be based on NXP’s popular i.MX application platform.
OpenHW Group seeks to offer open-source cores, related IP, and other tools. Image from OpenHW Group
According to OpenHW Group, Core V is "a series of RISC-V-based open-source cores with associated processor subsystem IP, tools and software for electronic system designers."
Tapeout of the (yet-to-be-designed) SoC will happen during the second half of 2020.
The SoC will feature a RISC-V core IP 64-bit (1.5GHz) CV64A CPU along with a companion 32-bit CV32E coprocessor. It’s also expected to pack 3D and 2D GPUs, a MIPI-DSI high-speed serial interface with CSI display, and a camera I/O.
OpenHW Group claims that they employ best practices in silicon and FPGA-optimized implementation for core IP in the CORE-V family. Image from OpenHW Group
OpenHW Group also plans to include:
- PCIe connectivity
- GigE MAC
- USB 2.0 interfaces
- Support for (LP) DDR4
- Multiple SDIO interfaces
- A range of peripheral blocks
- Hardware security blocks
Parallel Ultra Low Power (PULP) Platform
The open-source 64-bit CV46A CPU and 32-bit CV32E were developed at ETH Zürich as part of the institutions' PULP (Parallel Ultra Low Power) platform. The PULP platform is designed to bring scalable, energy-efficient hardware and software systems with widely-tunable performance.
PULP platform. Image from PULP Platform
ETH Zürich explains, “The aim of PULP is to satisfy the computational demands of IoT applications requiring flexible processing of data streams generated by multiple sensors, such as accelerometers, low-resolution cameras, microphone arrays, and vital signs monitors.”
Engineers at ETH Zürich produced several RISC-V cores under the project, including:
- 64-bit, 6-stage Ariane
- 32-bit, 2-stage Zero-riscy/Micro-riscy
- 32-bit, 4-stage core RI5CY.
The OpenHW Group based its 64-bit CV46A CPU on ETH’s Ariane processor, which transfers that level of energy efficiency and scalability over to the Core-V Chassis evaluation SoC.
RISC-V based Ariane CPU. Image from Github, Ariane Documentation
The 32-bit CV32E also borrows from ETH’s RISCY (RV32IMFCXpulp) RISC-V 4-stage core IP CPU, which improves performance for signal processing applications.
In a recent press release, OpenHW group chairman and NXP's VP of software engineering Rob Oshana stated, “NXP is thrilled to be a key contributor to the CORE-V Chassis project leveraging our world-class i.MX platform. We see the CORE-V Chassis project as a natural evolution towards enabling OpenHW Group open-source RISC-V cores for high-performance embedded processing.”
Members and Partners
Along with NXP, other tech companies that have joined OpenHW Group’s ambitious endeavor include Alibaba, Huawei, Silicon Labs, Mythic, OneSpin, Metrics, Imperas, UltraSoC, and more.
OpenHW Group members. Image from OpenHW Group
OpenHW Group has also drawn some partners to further their project as well, including the Eclipse Foundation, IBM Cloud, the Fossi Foundation, Publitek, PWC, and Norton Rose Fulbright, among several others.
Call for Participation
The Core-V Chassis evaluation SoC will form the foundation for further multi-core evaluation SoCs. OpenHW Group states that the announcement of the upcoming platform is an open call for others in the industry to join their project.
“The CORE-V Chassis project will help validate that serious silicon development is possible utilizing the ethos of open-source hardware, IP, and tools,” stated OpenHW Group CEO Rick O’Connor.
“With the tape out of a functional evaluation SoC during the 2nd half of 2020, we will demonstrate that the open hardware mindset is as capable and dependable as any of today’s closed-source alternatives.”