The RISC-V World Sees Changes, Milestones, and Innovations

In fifteen years, RISC-V has gone from an academic project at UC Berkeley to one of the major technological trends in compute. The ISA has since flourished in an era that appreciates its royalty-free, open-source building blocks.

RISC-V's modular approach allows anyone, anywhere, to benefit from IP contributed and produced by RISC-V. Image used courtesy of Siemens

In recent weeks, RISC-V has celebrated several notable wins, from major organizational announcements to new RISC-V-based technologies hitting the market. 

RISC-V’s 15-Year Anniversary

In honor of RISC-V’s recent 15-year anniversary, SiFive published a brief history and optimistic forecast on the future of the ISA.

In 2010, RISC-V was born from the Parallel Computing Laboratory (Par Lab) at UC Berkeley. At the time, the ISA presented a new approach that avoided legacy instruction complexity to achieve modular scalability. Over time, the architecture’s open nature drove broad adoption, now present in billions of devices and backed by more than 4,500 members in 70 countries. 

SiFive itself was founded by RISC-V’s creators and has translated this architecture into commercially viable IP cores ranging from minimal embedded controllers to high-performance vector processors. To date, its technology stack has shipped in over two billion devices and includes proprietary contributions like WorldGuard and vector-matrix extensions.

As proprietary ISAs raise concerns over vendor lock-in, SiFive anticipates that industry leaders will increasingly rely on RISC-V to decouple hardware design from legacy constraints and to enable full-stack hardware customization.

New CEO for RISC-V International

RISC-V International, the leading organization driving the RISC-V movement, recently underwent a leadership shift, appointing Andrea Gallo as its new CEO.

Andrea Gallo (left) and Jeff Child (right) at Embedded World 2025.

The RISC-V board selected Gallo based on his technical fluency and track record of driving multilateral collaboration in open computing environments. Before his appointment as CEO, Gallo previously served as vice president of technology at RISC-V and held leadership roles at Linaro and STMicroelectronics, where he focused on open-source development and cross-industry collaboration. 

Now, as CEO of RISC-V International, Gallo intends to scale technical and educational resource access, establish a formal RISC-V certification program, and increase member engagement across sectors and geographies. He also plans to expand coordination with the RISC-V Software Ecosystem (RISE) initiative to improve developer tooling and streamline integration across platforms. 

SiFive and Kinara Team Up

SiFive and Kinara recently introduced a USB-based development module that provides bare-metal access to the SiFive X280 RISC-V vector processor. 

The HiFive Xara X280 integrates Kinara’s Ara-2 SoC, which includes dual 64-bit SiFive X280 cores and support for real-time vector processing, floating-point computation, and tensor operations. In this module, the X280 cores interface directly with Kinara’s neural processing units, delivering up to 40 TOPS, and support transformer-based models such as LLaVA and LLaMA.

Kinara's Ara-2 processor. Image used courtesy of Kinara

Together, this architectural integration is said to unlock high-throughput inference for generative AI workloads. By decoupling host dependencies and offering direct access to the processor IP, the Xara board allows early-stage performance evaluation and vector software development. Availability begins in late Q2 2025.

Keysom Introduces Design Exploration Platform

Keysom recently announced its new Core Explorer, a design-space exploration platform for processor architecture development. 

Supporting real-time customization, comparison, and RTL generation through a no-code interface, the system permits granular architectural control with features like instruction set selection, pipeline staging, memory mapping with PMP, and cache/MMU integration. Users can configure parameters such as data width and branch prediction to optimize for performance, area, or power. The platform then outputs synthesizable RTL and deployable FPGA bitstreams along with verification reports and benchmarking metrics to accelerate the design loop.

Keysom Core Explorer layout. Image used courtesy of Keysom

According to Keysom, in a 130-nm silicon implementation of AES-256, the tool produced a 70% area reduction and a 40% drop in energy consumption by optimizing logic and memory trade-offs. Part of this is due to the system’s integrated smart compiler that adapts design configurations to evolving workloads. Meanwhile, the device also supports both cloud and on-premise deployment and has built-in SDK and HDK resources that provide HAL, RTOS, and simulation support.

What's Next for RISC-V?

In SiFive's anniversary recap of the ISA, the company claimed that “RISC-V is no longer a question of 'if' but 'when.'” That is, the company sees RISC-V emerging as the top ISA, even over long-standing legacy ISAs that now hold dominance in the computing market. The company also sees the most RISC-V growth occurring in AI and embedded market segments, with its power efficiency, scalability, and customizability making it appealing for matrix and vector operations, among many other applications.