Samsung Foundry Solidifies Partnerships With Major EDA Companies
At this year’s Samsung Foundry Forum, the company revealed how it is strengthening ties with Synopsys, Cadence, and Ansys.
This year, Samsung took to its Foundry Forum to divulge the company’s near-term and long-term plans for its foundry business.
Samsung made several announcements at this year’s Foundry Forum. Image courtesy of Samsung
For one, the company highlighted its plans to expand the applications of its 2-nanometer (nm) process and specialty process. Samsung also announced its intentions to enhance fabless support for its customers through solidified relationships with major EDA companies. In this piece, we’ll look at some of the major partnerships that Samsung established with EDA groups such as Synopsys, Cadence, and Ansys.
One of the major EDA players that Samsung fortified its ties with at this year’s Foundry Forum is Synopsys.
The companies recently expanded their agreement to jointly develop a wide-ranging portfolio of intellectual property (IP). With the intent to minimize design risk and speed up silicon success for various applications, this collaboration has enhanced Synopsys' IP offering for Samsung's advanced processes, including 8LPU, SF5, SF4, and SF3. Synopsys is also optimizing IP for Samsung's SF5A and SF4A automotive process nodes to meet stringent temperature and reliability requirements.
A Synopsys-Samsung silicon wafer. Image courtesy of Synopsys
Synopsys and Samsung Foundry are also helping chipmakers accelerate the design of 2.5D and 3D multi-die systems on Samsung's most advanced process technologies. The groups are offering certified EDA reference flows, including Synopsys 3DIC Compiler and UCIe IP for die-to-die connectivity, to help designers develop multi-die systems on Samsung Foundry's 5nm, 4nm, and 3nm processes.
Other notable collaborations between Synopsys and Samsung Foundry include the development of an optimized design flow for Samsung Foundry's SF2 process and a new reference flow for radio-frequency integrated circuit (RFIC) design developed with Samsung Foundry for its 14LPU process technology.
Samsung also announced plans to partner with Cadence at this year’s Foundry Forum.
First, the companies announced that they will be leveraging Cadence’s Integrity 3D-IC platform to design next-generation multi-die packages. Specifically, they aim to provide reference flows, package design kits, and the Samsung 3D CODE standard to Cadence’s tools to eliminate design challenges such as flow complexities and system-wide integrity issues.
Following this announcement, Cadence revealed that Cadence Design Systems has developed a comprehensive, certified backside implementation process to support Samsung Foundry's SF2 process node. The Cadence RTL-to-GDS flow, optimized for Samsung Foundry's 2nm process technology, includes various solutions and systems such as the Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution, among others. The backside routing enhances PPA results and alleviates congestion on the frontside layers, making it suitable for power distribution networks, clock tree nets, and signal routing.
Finally, the groups announced that Cadence’s digital and custom analog workflows are now certified for Samsung Foundry’s SF2 and SF3 processes. With the certified flow, designers using Cadence will have access to features such as cell-swapping support, mixed-row solutions, mask-shifted cells, and support for various rectilinear standard cells to achieve higher density and reliability in these designs.
The final EDA player Samsung announced partnerships with at this year’s Foundry Forum is Ansys.
In the aforementioned RFIC design developed by Samsung and Synopsys, Ansys provided a “golden signoff electromagnetic analysis” through its RaptorX Electromagnetic Modeling Family, Exalto Electromagnetic Extraction and Signoff, and Ansys VeloceRF Inductor and Transformer Design Tools.
The new reference flow from Ansys and Samsung. Image courtesy of Ansys
Ansys later unveiled that it had achieved certification for its RedHawk-SC and Totem power integrity signoff solutions for Samsung’s latest 2nm silicon process technology. Additionally, Samsung Foundry certified Ansys’ thermal integrity and verification platform for Samsung’s multi-die packaging technologies. With this collaboration, Samsung Foundry and Ansys hope to improve the thermal reliability and performance of 2.5D and 3D ICs in Samsung’s processes.
Samsung Strengthens Its Semiconductor Leadership
Samsung is pursuing several approaches to advance its process nodes and capabilities. By improving workflows and collaborations with the industry’s major EDA players, the company is ensuring that more advanced ICs are built on Samsung Foundry’s processes. This move strengthens Samsung's place in the semiconductor industry and makes the design of next-generation chips more accessible to all.