Scaling Down to 3nm Will Require Advances in Fabrication Technology

March 17, 2021 by Jake Hertz

Keeping up with Moore's law at semiconductor fabs is not only an economic struggle. It's an issue of process control technology, too.

The semiconductor industry thrives on a very straightforward concept: make the transistor smaller. From the invention of the transistor until now, this approach seemed like a bottomless pot of gold with each new node bringing more money. 


Moore’s Law has driven the semiconductor industry to this point.

Moore’s Law has driven the semiconductor industry to this point. Image used courtesy of The Next Platform

Now, as manufacturers approach 3nm, fabrication and economic barriers have made this same approach more complicated. AAC had the chance to sit down with Applied Materials, a company that develops equipment for semiconductor fabs, to hear about new process controls it hopes can breathe life back into the semiconductor industry. 


The Race to Shrink Nodes Is Expensive 

While design costs have historically increased with new nodes, those costs are now growing exponentially. 

According to McKinsey and Company, the total cost of designing an IC at the 16nm node, including architecture, verification, and IP qualification, cost about $104 million. Skip forward to 5nm and we’ve reached $297 million. $500 million is on the horizon for 3nm. 


The cost of R&D and manufacturing of new IC nodes has grown exponentially

The cost of R&D and manufacturing of new IC nodes has grown exponentially. Image used courtesy of McKinsey and Company

Yet, in many ways, the only thing more expensive than scaling transistors down to the 3nm node is creating the manufacturing equipment that can physically produce these transistors. The same report from McKinsey tells us that the cost of building and equipping a fab at the 16nm node was $1.3 billion. At 5nm, we’ve reached $5.4 billion, and $10 billion could be in the future for 3nm.

Many of these equipment costs come from the need for new tooling to support smaller node manufacturing; for instance, while EUV tools are now a crucial (and costly) necessity for smaller nodes, they didn’t exist for large node sizes. 

The technical and economic challenges that face semiconductor fabs have grown so large that only massive corporations can even afford to have skin in the game


The Cost of Fab Efficiency

An immediate corollary of this increasing semiconductor design and manufacturing cost is that efficiency has become more important than ever. Think of it this way: because operating a fab can cost millions of dollars a day, any downtime is detrimental. For this reason, many fabs keep millions of dollars worth of wafers as idle inventory since they’d rather incur these costs than the costs associated with downtime. 


Fab utilization vs. break-even time with different levels of subsidization

Fab utilization vs. break-even time with different levels of subsidization. Image used courtesy of McKinsey and Company

The McKinsey and Company report shows that without government subsidy, a fab at the 5nm would take over five years to break even on the investment, even if it were running at 100% utilization. When utilization decreases to 50%, even a fab that’s been subsidized up to $2 billion will take over 10 years to break even. 

These steep economic barriers have disincentivized companies from even getting involved, further consolidating the industry onto the backs of a few wealthy companies and nations. 


Applied Materials Streamlines Wafer Defect Detection

These fab facilities are continually looking for ways to improve efficiency in terms of speed and yield. Applied Materials is aiming to solve this problem by implementing AI and data science into the wafer inspection process


Defect detection

Defect detection can be a costly process in modern-day semiconductor facilities. Image used courtesy of Applied Materials

One of their platforms, dubbed Enlight, leverages data science and optics to perform more advanced wafer inspections. By collecting more yield-critical data, the company believes it can reduce the cost of capturing critical defects by three times and improve yields in the same process. 

Another element of process control, the SEMVision System, is an eBeam review technology that trains the Enlight system using a third element: ExtractAI.

The ExtractAI system uses artificial intelligence to distinguish yield defects from generic noise that high-end scanners create. The system works so well, in fact, that the company reports the ability to identify all of the potential defects on a wafer after reviewing only 0.001% of the samples. 


Applied Materials

The three elements—Enlight (left), ExtractAI (center), and SEMVision (right)—use optics to capture more yield data and AI to quickly classify wafer defects. Image used courtesy of Applied Materials

A Solution to 3nm Production?

As fab houses are tasked with the feat of scaling to 3nm, it's essential that equipment identifies wafer defects more quickly and efficiently. Tools like those rolled out by Applied Materials, it seems, may lead the charge in decreasing the cost of this endeavor while also keeping production cycles on time.