The Cray-1 Chipset: An 800 MHz Supercomputer Built From Four Chip Types

On April 1, 1976, Los Alamos Scientific Laboratory in New Mexico installed serial number 001 of the Cray-1. By August, Computerworld called it "the world's most expensive love seat" for the padded bench that hid its power supplies. Seymour Cray had built it in Chippewa Falls, Wisconsin, from a parts list that would fit on an index card. 

A Cray-1 on display at the Science Museum in London. Image used courtesy of Irid Escent via Wikimedia Commons (CC BY-SA 2.0)

Richard Russell's 1978 account in Communications of the ACM counts four chip types, all emitter-coupled logic: high-speed and low-speed versions of a dual 5/4 NAND gate, a bipolar register chip with a six-nanosecond cycle time, and a 1,024-bit bipolar memory chip, which Cray's own hardware manual credits to Fairchild and its Isoplanar process. From those, Cray built a 64-bit vector computer with a 12.5-nanosecond clock period (80 MHz), while the MOS 6502 ran at 1 MHz.

One Gate in a 16-Pin Flatpack

Cray's hardware reference manual describes the high-speed gate as an ECL circuit with four or five inputs and both true and inverted outputs, with one of each packaged together in a 16-pin hermetically sealed flatpack; the CPU built every latch, adder, and subtracter from it. Propagation delay ran between 0.5 nanoseconds and one nanosecond, with edge speeds of one nanosecond or less. While Cray's documents never name the vendor's part number, collectors have identified it as Fairchild's 11C01, listed in Fairchild's 1975 catalog as a dual 5-4 input OR/NOR gate with a 0.7-nanosecond typical delay and 125 mW per package.

Russell, drawing on a 1975 talk Cray gave to prospective customers, explained that using only simple gates and terminating both outputs of every one meant the machine presented "just a purely resistive load to the power supply," with no switching transients on the rails. ECL transistors never saturate, and differential current steering draws nearly the same supply current whether a gate sits high or low. Each module carried two 6-by-8-inch five-layer boards on a copper plate, with up to 144 flatpacks per board, and dissipated as much as 65 W. The full machine of 1,662 modules drew roughly 115 kW, all of it carried away by Freon flowing through cast-aluminum cold bars.

The low-speed gate was a MECL 10K-compatible version of the same 5/4 gate. Cray used it for address fanout on the memory modules, where its speed was adequate, and it drew less power. Russell also noted that 10% to 20% of the IC packages in the machine were there only to pad signal lines and equalize path delays.

Isoplanar Memory at 50 Nanoseconds

The main memory held up to 1,048,576 words of 72 bits, 64 data bits plus eight check bits, in 16 independent banks. Cray's manual describes its building block as a bipolar 1,024 x 1 LSI chip "developed by Fairchild using the isoplanar technology," with a maximum 50-nanosecond read/write cycle and ECL-compatible levels. Fairchild sold the part as the F10415, rated in its 1977 data book at 25 nanoseconds typical read access and 0.5 mW per bit. A fully populated memory needed 73,728 of them, one bit per module.

A Cray-1 memory board. Image used courtesy of Jud McCranie via Wikimedia Commons (CC BY-SA 4.0)

Isoplanar was the work of Fairchild's Douglas Peltzer, who filed the patent in February 1971. Conventional bipolar processes isolated neighboring transistors with deep p-type diffusions; Isoplanar replaced them with thermally grown oxide, which let the base and collector contacts abut the isolation. The oxide halved the transistor area and cut parasitic capacitance, with Fairchild's data book noting that the 1,024-bit TTL RAM it introduced in 1972 wouldn’t have been practical with the older junction isolation. 

Serial number 001 shipped with parity checking only, and during its six-month Los Alamos trial, it logged 152 memory parity errors. A 2010 analysis by Eugene Normand and colleagues in IEEE Transactions on Nuclear Science concluded that atmospheric neutrons had flipped the bits, making the Cray-1 the first recorded case of ground-level single-event upsets. By October 1976, Cray Research had added single-error-correcting, double-error-detecting memory to the design.

What Came After

Twelve wedge-shaped columns in a 270° arc kept every backplane connection to two 18-inch twisted pairs joined by a solder sleeve, and the gap in the arc left room, in Russell's words, "for a reasonably trim individual" to get inside. The National Center for Atmospheric Research paid $8.86 million for serial number 3 in 1977 and got a machine Russell rated at 138 MFLOPS sustained and 250 MFLOPS in bursts.

Cray's 1982 X-MP moved to bipolar gate arrays with 16 ECL gates each, and the 1985 Cray-2 packed similar arrays into three-dimensional modules immersed in Fluorinert. Serial number 001 worked for 13 years and now sits in the Chippewa Falls Museum of Industry and Technology.

Did you ever run code on a Cray-1, or wrestle with ECL at these speeds? Tell us about it in the comments below.