Inside a Multi-$Billion IP Engine Driving IC and EDA Innovations

The semiconductor landscape is changing faster than ever. Chips now power everything from AI to advanced automotive systems. At the heart of this rapid revolution is semiconductor intellectual property (IP).

In this episode, Daniel Bogdanoff sits down with John Koeter formerly of Synopsys. They explore how pre-verified silicon blocks accelerate chip design. They also discuss the massive shift toward multi-die systems and the future role of AI in engineering.

Accelerating Chip Design with Pre-Verified IP and Multi-Die Architectures

As Moore's law slows down, chip designers face extreme physical challenges. Designing a complex system-on-chip (SoC) from scratch is no longer viable. Companies rely on proven IP blocks to speed up time-to-market and ensure silicon success.

Today, the industry is transitioning to multi-die systems. Instead of one massive chip, designers stack multiple specialized chiplets in advanced packages. This transition introduces complex thermal and power challenges that require highly accurate modeling.

• System on a Chip (SoC): An integrated circuit that combines all necessary electronic circuits and parts on a single chip.
• Multi-Die Systems (Chiplets): An architecture where multiple specialized dies are combined in a single package to maximize performance.
• Model to Hardware Correlation (MHC): The practice of ensuring pre-silicon simulation models accurately predict real-world post-silicon behaviors.

Managing thermal distribution is the biggest hurdle in 3D IC design. Stacking chips creates intense hotspots. These hotspots can crack or delaminate packages if unmanaged. Engineers must use advanced simulation tools to model these thermal characteristics early in the design cycle.

Meet John Koeter

John Koeter was the Senior Vice President of IP at Synopsys. He led the company's multi-billion-dollar intellectual property business, driving critical innovations in EDA and silicon design. Since the time of this recording, Koeter has retired.

John began his career as an R&D engineer at Texas Instruments. During his time at TI, he helped design early chips for pioneering mobile phone networks like Nokia. He also managed ASIC products, wearing multiple hats across layout, testing, and customer applications.

An avid science fiction fan, John loves studying how technology shapes society. Throughout his three-decade career, he has championed adaptability and passion as the ultimate keys to engineering success. John holds an electrical engineering degree from Cornell University.