Technical Article

Analyzing a Current-Mode-Controlled Buck Converter in LTspice

November 08, 2023 by Robert Keim

In this article, we use voltage waveforms to explore the electrical behavior of key subcircuits within a CMC buck converter.

In the previous two articles, we explored the design principles and basic operation of the current-mode-controlled (CMC) buck converter shown in Figure 1. In this article, we’ll use simulations to perform a fairly granular analysis of the circuit’s electrical behavior.


LTspice schematic of a peak-CMC buck converter.

Figure 1. A CMC buck converter implemented in LTspice.


Startup Behavior

There are two major differences between my LTspice implementation and the circuit I based it on:

  1. The lack of slope compensation, which we discussed at the end of the previous article.
  2. My inclusion of additional circuitry that can help jump-start the regulator, which we’ll discuss now.

If you inspect Figure 1, you’ll see that the output of the comparator is not connected directly to the SR latch’s reset line. The PWMR signal, which is controlled by the arbitrary behavioral voltage source B1, drives the reset line instead. With the help of the voltage source labeled TMR (for “timer”), B1 initially connects PWMR to an inverted version of the square wave that sets the latch. The TMR voltage gradually rises from 0 to 5 V; at t = 1 ms after the start of the simulation, it crosses 2.5 V.

This condition causes B1 to disconnect PWMR from the inverted oscillator signal and connect it to the output of the comparator. It might sound complicated, but it’s just a way of allowing the feedback loop to do its work—it forces the regulator to start switching and generating some current and voltage action.

You won’t need the startup-assistance circuitry if you duplicate my circuit exactly, but it’s possible that even minor adjustments will interfere with startup, and if the regulator’s not switching you can’t effectively diagnose and redress problems.

Figure 2 shows my schematic without startup-assistance circuitry. We’ll use this version of the schematic for the simulations discussed in this article. Note that the output of the comparator connects directly to the latch’s reset pin.


LTspice schematic of a peak-CMC buck converter without startup-assistance circuitry.

Figure 2. CMC buck converter without startup assistance circuitry.


Output Convergence

Figure 3 shows the voltage regulator's transient behavior after startup.


Voltage behavior of the CMC buck converter directly after startup. Output voltage briefly spikes, then settles at the desired level.

Figure 3. Transient behavior of the CMC buck converter after startup.


The regulator needs only about 100 μs to converge with high precision on the desired output voltage. Ripple magnitude is fairly low, as we can see in Figure 4.


Output ripple for a simulated CMC buck converter.

Figure 4. CMC buck converter output ripple.


The Error Amplifier

As I explained in the preceding article, the error amplifier doesn’t have a DC feedback path, and will therefore act like a comparator if the output is slowly moving above or below the desired voltage. Under normal conditions, however, the regulator loop is locked onto an output voltage. The differences between VFB and VREF are then caused by small, frequently occurring amplitude variations. This means that the error amplifier acts like an amplifier, not a comparator, as we see in Figure 5.


Voltage waveforms for the error amplifier in a simulated CMC buck converter.

Figure 5. Normal error amplifier behavior in a CMC buck converter.


The Comparator and the SR Latch

The CONTROL signal becomes the threshold that allows inductor current to govern PWM action. Let’s take a look at how this works.

The loop is designed such that the CONTROL signal is in the proper range relative to the IND_RAMP signal. The system’s oscillator is connected to the latch’s set pin. At the beginning of each switching cycle, the oscillator transitions to logic-high, causing the latch’s Q-output to transition to logic-high in turn. This is known as “setting” the latch.

If Q is high, the primary power switch (M1) is on. When M1 is on, current is flowing through the inductor and IND_RAMP is ramping up. When the voltage representing inductor current crosses the threshold level established by CONTROL, the comparator output goes high. This causes the latch’s Q-output to transition to logic-low, “resetting” the latch. Now M1 is off, and inductor current starts ramping down. The oscillator eventually sets the latch again, and the cycle repeats.

In short, the following events occur in sequence over the course of a single switching cycle:

  1. The oscillator goes logic-high.
  2. The latch’s Q-output goes logic-high. M1 is now on.
  3. Inductor current ramps up.
  4. The voltage representing inductor current crosses the CONTROL threshold.
  5. Comparator output goes high.
  6. The latch’s Q-output goes logic-low. M1 is now off.
  7. Inductor current ramps down.

The multi-pane plot in Figure 6 tells the story fairly well, though you might have to ponder it for a little while.


Voltage waveforms for the comparator and SR latch in a CMC buck converter.

Figure 6. Voltage behavior for the comparator and SR latch over a 0.040 ms period.


The version in Figure 7 shows the timing relationships a bit more clearly: the logic-high portion of the PWM signal begins with the rising edge of the oscillator signal and ends when IND_RAMP reaches CONTROL, causing the comparator to reset the latch.


Voltage waveforms for the comparator and SR latch in Figure 6, but over a shorter time period.

Figure 7. Voltage behavior for the comparator and SR latch over ~0.015 ms.


The duty cycle determines output voltage, but the control loop doesn’t have to rely entirely on output voltage to adjust the duty cycle properly. Instead, the output voltage provides the threshold via the error amplifier. The inductor current provides the fundamental mode of controlling the power switch (hence current-mode control).

The linkages between comparator output and switch state, and then between switch state and inductor current, sometimes cause the IND_RAMP signal to zig-zag above and below the CONTROL signal. This, in turn, causes spurious transitions in the PWM signal.

These transitions don’t seriously impair the regulator’s functionality, but it’s worth noting that—at least for simulation purposes—you can mitigate them by reducing the comparator’s hysteresis voltage. The previous plots were generated with a hysteresis voltage of 10 mV. In Figure 8, it’s been reduced to 1 mV.


Voltage waveforms for the comparator and SR latch in Figures 6 and 7, but with 9 mV less hysteresis.

Figure 8. Voltage behavior for the comparator and SR latch with hysteresis reduced from 10 mV to 1 mV.


These results look a lot better. Still, I consider this hysteresis adjustment to be a solution only in the context of my noise-free simulation environment. In the real world, you’ll want to set the hysteresis of your circuit based on the amount and type of noise in your application.



In this article, we examined voltage waveforms associated with the output stage, error amplifier, and PWM generator of a CMC buck converter. I hope that you found this discussion informative, and that you enjoyed thinking about the complex signal and component interactions that make robust switch-mode regulation possible.


Featured image used courtesy of Adobe Stock; all other images used courtesy of Robert Keim