Designing a Current-Mode-Controlled Buck Converter in LTspice
In this article, we’ll learn about current-mode control (CMC) for switching regulators by examining the layout of an example circuit in LTspice.
My previous article provided a theoretical overview of current-mode control (CMC) as a technique for achieving high-performance voltage regulation in DC-DC converters. Now we’ll use LTspice to take a closer look at how these circuits actually work.
I’ve created an LTspice schematic of a CMC buck converter (Figure 1) to help us examine CMC design principles and operation. This circuit is a closed-loop system that uses voltage and current feedback to lock onto an output voltage.
Figure 1. LTspice schematic of a peak-CMC buck converter.
This implementation is based on the peak-CMC buck converter in Figure 6 of this Texas Instruments document: “Understanding and Applying Current-Mode Control Theory.” There are a few important differences, which I’ll explain as they become relevant. For now, let’s examine the components of this schematic and how they contribute to the circuit’s function.
RSENSE and DIFF-AMP
A current-feedback signal is generated by amplifying the voltage across a current-sense resistor (RSENSE) that is in series with the inductor (L). For the sake of convenience, I’m using an arbitrary behavioral voltage source (DIFF-AMP) instead of the SPICE version of a differential amplifier. The DIFF-AMP output is equal to the voltage across RSENSE multiplied by ten.
The total current-to-voltage gain can be calculated as follows:
Feedback Voltage and Error Amplifier
The output voltage is connected to a resistive voltage divider composed of RFB1 and RFB2. This divider delivers a feedback voltage (VFB) to a compensated error amplifier consisting of VREF, U1, RCOMP, CCOMP, and CHF.
Completing the Control Loop
A1 and A2 complete the control loop by using the current-feedback signal and the voltage error signal to generate appropriate gate-drive waveforms for the switches, which in this schematic are implemented as NMOS transistors. A1 is a Schmitt-trigger buffer that functions as a comparator because it has a differential input, and A2 is an SR latch. LTspice calls it SRFLOP.
The Power Stage
M1, M2, L, RSENSE, and COUT belong to the power stage. Note that the COUT value (Figure 2) includes 1 mΩ of ESR.
Figure 2. COUT (with ESR included) for CMC buck converter simulation.
I already discussed the buck topology in previous articles, so I won’t spend too much time on it here. There are some aspects of this particular circuit’s power stage I’d like to comment on, however, namely the gate-drive voltage for M1 and the presence of two switches instead of a switch and a diode. We’ll talk about these in the next two sections.
M1 and M2 can be seen toward the left-hand side of Figure 3, which shows the buck converter’s power stage.
Figure 3. The power stage portion of the CMC buck converter schematic in Figure 1.
Boosting M1 Gate Drive
As I mentioned above, we’re using an NMOS transistor for the power switch (M1). We can’t just drive the gate with any old logic signal as though the FET’s source were at ground.
My primary logic voltage in this circuit is 5 V. Since VOUT is also 5 V, we can readily conclude that 5 V is not enough gate voltage to turn this FET into an effective switch. In any case, we want the gate voltage to be higher than VIN, not just higher than VOUT.
A physical implementation can resolve this complication by including charge-pump circuitry to boost the gate-drive signal. With an LTspice implementation, the solution is even simpler: I just tell the SR latch to use 15 V as a logic-high voltage (Figure 4).
Figure 4. Logic-high voltage definition for the SR latch (SRFLOP).
The technique of using a switch instead of a diode is called synchronous rectification. This approach is associated with a long list of benefits: to quote a TI app note on the topic of synchronous rectification in power converter design, it “improves efficiency, thermal performance, power density, manufacturability, and reliability, and decreases the overall system cost of power supply systems.”
With an endorsement like that, it’s difficult to defend my use of diodes in switcher simulations. Because an FET driven into full conduction drops less voltage than a forward-biased diode, synchronous rectification is preferable in real-life applications; when the goal is to explain fundamental principles rather than optimize performance, however, diodes do seem a bit simpler. On the other hand, maybe I’m just nostalgic for pre-1990s circuit design.
In any event, the second switch must have its own drive signal, because the low-side FET (M2 in my schematic) needs to block current when the high-side FET (M1) is conducting current, and vice versa. I would normally find this requirement slightly annoying, but in this case it’s no problem at all—we’re already using an SR latch to generate the PWM signal, and the latch’s Q-not output is exactly what we need for the second FET.
Switching regulators are known for converting voltages with minimum power wastage, and it’s a bit disappointing that we have to place a resistive element in a potentially high-current circuit path (Figure 5). Overall, though, this is a small price to pay for the benefits of current-mode control.
Figure 5. Current-sense resistor (RSENSE).
The value of RSENSE (10 mΩ) is an attempt to balance efficiency and accuracy—we want to reduce power dissipation while generating voltages large enough to compete well with noise and amplifier non-idealities. My “amplifier” is a purely mathematical component, and SPICE circuits don’t have noise unless you deliberately include it, so we could use a much smaller resistor in this simulation if we wanted to.
In a physical circuit, something like the INA240 would be a good choice for amplifying the RSENSE voltage.
To Be Continued…
In this article, we analyzed our example CMC buck converter primarily through its schematic. Next time, we’ll improve our understanding of the circuit by generating voltage waveforms in LTspice.
All images used courtesy of Robert Keim