Technical Article

Charge-Coupled Device Clocking Techniques for CCD Readout

April 02, 2020 by Robert Keim

This article continues the Image Sensor Technology series by examining details involved in the movement of light-generated electric charge within a CCD.

A CCD is a light-sensitive charge-transferring device, and it’s time for us to take a closer look at how exactly a circuit designer directs the movement of optical information from individual pixel locations to the sensor’s output terminal. As explained previously, the fundamental means of performing CCD readout is the application of clock pulses.

If you'd like more context before moving on, consider learning more about CCD sensor types.


Not a Typical Clock Signal

I hesitate to use the term “clock” in this discussion because in my mind, a clock signal is almost always a logic-level waveform that interacts with typical digital circuitry.

CCD voltages are very much of the “nonstandard” variety. High-level clock voltages are often greater than what we use for CMOS logic, and low-level voltages often extend below ground.

I chose a few CCD datasheets at random to give you some examples of what to expect. Make sure you read the previous article if you don’t understand what I mean by “frame transfer” and “interline transfer.” 

KAI-1020 from ON Semiconductor: This is an interline-transfer device with a resolution of 1000 × 1000 active pixels. Control voltages range from –9 V to +15 V. However, the control signals applied to the chip use 5 V logic; internal drivers translate the logic signals to the voltage levels required by the charge-transfer gates.


I thought you might enjoy this slick 3D representation of an interline-transfer CCD, taken from the datasheet for the KAI-1020.


ICX059CL from Sony: This is a 752 × 582 pixel, interline-transfer CCD intended for monochrome video cameras. If I’m understanding the datasheet correctly, it uses 15 V to transfer charge packets from photodiodes to vertical shift registers, –8.5 V to 0 V for vertical-transfer clocks, and 0 V to 5 V for horizontal transfer. The diagram below conveys the overall architecture of this device.


Diagram taken from the ICX059CL datasheet.


TC281 from Texas Instruments: This 1000 × 1000 pixel image sensor uses the frame-transfer architecture. Most of the clocks have a low level of –10 V and a high level of +2 V.


The portion marked with the × symbol is the array of light-sensitive pixels, and the lower half is the storage array. Diagram taken from the TC281 datasheet.


Readout-Clock Configurations

Let’s return to the semiconductor level and talk about how exactly we persuade charge packets to move from pixel to output terminal. We know that this is achieved by applying sequences of voltages that in turn create sequences of potential wells and potential barriers, but it turns out that there are several different ways of creating the necessary variations in potential.


Four-Phase Clocking

The most straightforward method uses four clock phases. We’ll consider the four-phase approach in some detail, and then I’ll briefly mention other schemes.

As shown in the following diagram, a four-phase CCD has four gates in every pixel. Thus, four separate clock signals applied to four distinct sections of the pixel are needed to move a charge packet into the adjacent pixel.



(Note that if this were an interline-transfer CCD, we might say something like “shift-register sections” rather than “pixels,” since charge packets don’t move through photoactive regions in the interline-transfer architecture.)

The process starts at what we’ll call Stage 1. Clock A and Clock B are high, and Clock C and Clock D are low. (Remember that “high,” meaning higher voltage, creates a potential well that attracts electrons, and “low” creates a potential barrier that blocks electrons.)

Before you continue, have a look at the following diagram and refer to it as we make our way through the next three stages.



  • In Stage 1, charge accumulates in the potential well under Gates A and B, and it can’t move because it is blocked by the barrier under Gates C and D.
  • In Stage 2, Clock A goes low and Clock C goes high. Clocks B and D don’t change. This moves all the electrons one step to the right, because now there is a well under Gates B and C and a barrier under Gates A and D.
  • In Stage 3, Clock B goes low and Clock D goes high. We’ve pushed the electrons one step to the right again, because now the potential well is under Gates C and D.
  • In Stage 4, Clock A goes high and Clock C goes low. Now we have a potential well that extends from Gate D of one pixel to Gate A of the next pixel.
  • Stage 5 is the same as Stage 1. The charge is fully transferred to the adjacent pixel, and the cycle continues.


Three-, Two- , and One-Phase Clocking

The problem with the four-phase scheme is that sensor resolution is restricted by the need to have four gates in every pixel. We can decrease pixel size and therefore increase pixel density by reducing the number of clocks required for charge transfer, but in order to reduce the number of clocks, the applied voltages must become more complex.

Alternatives to four-phase control are three-phase, pseudo-two-phase, true-two-phase, and virtual-phase (i.e., single-clock) control. Regarding the CCD sensors mentioned above as examples, the KAI-1020 uses two-phase clocking, the ICX059CL uses four-phase clocking, and the TC281 uses a scheme that TI describes as “proprietary advanced virtual-phase” clocking.



Now that we have discussed control voltages and charge-transfer clock configurations, we’re ready to explore the analog output signal generated by a CCD image sensor. This will be the topic of the next article.