Design Project: Pulse-Width Modulation (PWM) Signal Generator
Analog Integrated Circuits
The design recommendation for this circuit is to make resistors R2 and R3 both equal to the resistance of the potentiometer Rpot2. This way, the full mechanical range of the potentiometer will be useful for adjusting duty cycle: fully turning it one way will just produce a 0% duty cycle, while fully turning it the other way will just produce a 100% duty cycle.
Explain why those resistor values need to be equal to achieve this optimum usage of pot range. Hint: it has something to do with the internal workings of the 555 timer IC.
The following modification may be made to the circuit to provide it with additional output current capability:
Here, six CMOS inverters (IC part number 4049) are ganged together in parallel to supply significantly more sourcing and sinking current capability than the LM339-with-pullup-resistor could on its own. Since CMOS logic gates are inherently on-or-off devices, they have no trouble handling the square wave output of the LM339.
Two questions here: first, why all the resistors at the outputs of the inverter gates? Why not just connect all the inverter outputs directly in parallel? Secondly, what value of resistor would you suggest at the output of each gate (R5 through R10)?
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