Verilog Parameterizable Adder Tree
Details
Category: Arithmetic Core
Created: March 17, 2018
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Stable
WishBone compliant: No
WishBone version: n/a
License: LGPL
Description
Parameterizable Verilog module that calculate sum of N variables. It works in streaming mode and can used in convolution (FIR) and in phased array systems.
