Simple Asynchronous Serial Controller in Verilog

Simple Asynchronous Serial Controller in Verilog


Category: Communication Controller

Created: September 17, 2002

Updated: January 27, 2020

Language: Verilog

Other project properties

Development Status: Stable

Additional info: FPGA proven

WishBone compliant: No

WishBone version: n/a

License: n/a


Simple asynchronous serial controller (aka UART). Includes 4
byte receive and a 4 byte transmit FIFO (FIFO size can be easily
adjusted). External baud rate generator (included). Very small.


- Implemented in Verilog
- Flow Control (CTS/RTS)
- 1 start bit, 1 stop bit, NO parity
- 4 byte receive FIFO
- 4 byte transmit FIFO
- Fully Synthesisable
- 102 LUTs in a Spartan II


This core is fully functional and completed.
It was verified in hardware in an XESS XVC800 FPGA prototype
board with a Maxim RS232 line driver.

This IP Core is provided by: - Solutions for your ASIC/FPGA needs -