Wishbone Asynchronous Memory Bridge
Details
Category: Memory Core
Created: November 18, 2009
Updated: January 27, 2020
Language: Verilog
Other project properties
Development Status: Alpha
WishBone compliant: Yes
WishBone version: n/a
License: LGPL
Description
This project provides a bridge between asynchronous external memory interfaces found on many processors and a WishBone bus. It is being used on the de1_olpcl2294_system project.
