Codezero Microkernel OpenRISC Port

Introduction

Codezero,

L4 microkernel architecture

Design principles

Benefits

The microkernel is the only component that runs in privileged CPU mode. Therefore it is the central point of trust on the platform, responsible for the overall security and stable operation of the system. The microkernel is kept rigorously small, therefore making the system secure and stable.

Codezero microkernel technical features

General features

• System partitioning with the concept of containers
• Fully capability-checked kernel provides:
  • Flexible and configurable resource management
  • Fine-grain security
• CML2-based kernel and system configuration interface
• Written in C using a familiar open-source coding style
• Support for the ARM architecture, including ARMv7, Cortex-A9
• Multicore enabled
• Portable design and structured layout
• Focus on embedded systems
• Open-source license option and development model

• Thread creation, destruction, and management of thread execution
• Address-space creation, deletion, and manipulation
• Interprocess communication
• Creation of virtual-to-physical address mappings
• Dynamic management of resource access via capabilities
• Userspace shared-memory synchronization
• Cache and TLB control
• System-on-Chip security, power, and error-recovery management

Real-time features

• The microkernel supports kernel preemption, i.e., even tasks running inside the microkernel may be preempted if their timeslice expires.
• All blocking operations are interruptible. A task sleeping on an IPC queue, a lock, or any waitqueue may be interrupted.
• Codezero has a priority-based scheduler. As such, timeslices are distributed based on the priorities.
• There are very few locks in the microkernel; consequently concurrency conflicts are avoided and kernel preemption is enabled most of the time.